From: Connor Abbott <cwabbott0@gmail.com>
Date: Mon, 27 Jul 2020 10:46:28 +0000 (+0200)
Subject: ir3: Validate bindless samp_tex correctly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3adc23f667b499d06f63d41a7973b26aed9d66df;p=mesa.git

ir3: Validate bindless samp_tex correctly

It's full instead of half precision, because the maximum number of
textures/samplers is much larger.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>
---

diff --git a/src/freedreno/ir3/ir3_validate.c b/src/freedreno/ir3/ir3_validate.c
index 58b5bee1e87..d094bd4becb 100644
--- a/src/freedreno/ir3/ir3_validate.c
+++ b/src/freedreno/ir3/ir3_validate.c
@@ -91,14 +91,17 @@ validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr)
 
 		/* Validate that all src's are either half of full.
 		 *
-		 * Note: tex instructions w/ .s2en are a bit special in
-		 * that the tex/samp src reg is half-reg irrespective of
-		 * the precision of other srcs.  The tex/samp src is the
-		 * first src reg when .s2en is set
+		 * Note: tex instructions w/ .s2en are a bit special in that the
+		 * tex/samp src reg is half-reg for non-bindless and full for
+		 * bindless, irrespective of the precision of other srcs. The
+		 * tex/samp src is the first src reg when .s2en is set
 		 */
 		if ((instr->flags & IR3_INSTR_S2EN) && (n < 2)) {
 			if (n == 0) {
-				validate_assert(ctx, reg->flags & IR3_REG_HALF);
+				if (instr->flags & IR3_INSTR_B)
+					validate_assert(ctx, !(reg->flags & IR3_REG_HALF));
+				else
+					validate_assert(ctx, reg->flags & IR3_REG_HALF);
 			}
 		} else if (n > 0) {
 			validate_assert(ctx, (last_reg->flags & IR3_REG_HALF) == (reg->flags & IR3_REG_HALF));