From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 22:54:07 +0000 (-0800)
Subject: Adding missing vexriscv CPU.
X-Git-Tag: 24jan2021_ls180~424^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ae4f8f2de7494411e5278b11dd7db1c0ae7389f;p=litex.git

Adding missing vexriscv CPU.
---

diff --git a/litex_setup.py b/litex_setup.py
index ffd8fd76..ff2777bf 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -43,6 +43,7 @@ repos = [
     ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)