From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 18 Mar 2015 17:54:22 +0000 (+0100)
Subject: mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it... 
X-Git-Tag: 24jan2021_ls180~2099^2~162
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3aee58f484a7b659b0d002f0e554a8d8bb87afbe;p=litex.git

mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)
---

diff --git a/mibuild/lattice/diamond.py b/mibuild/lattice/diamond.py
index dbbc99ae..3a12456c 100644
--- a/mibuild/lattice/diamond.py
+++ b/mibuild/lattice/diamond.py
@@ -40,6 +40,8 @@ def _build_lpf(named_sc, named_pc):
 def _build_files(device, sources, vincpaths, build_name):
 	tcl = []
 	tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device))
+	for path in vincpaths:
+		tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}")
 	for filename, language in sources:
 		tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"")
 	tcl.append("prj_run Synthesis -impl implementation -forceOne")