From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 13:56:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~178
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3af35113389510880fc7297ade1cd112a71bfd63;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 2aae637d5..f0293f43d 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -85,11 +85,12 @@ be operated on by the instruction.
 Thus, logically, we may set the following rule:
 
 * When a 5-bit CR Result field is used in an instruction, the
-  `inv, VLi and RC1` variant of Data-Dependent Fail-First
+  5-bit variant of Data-Dependent Fail-First
   must be used. i.e. the bit of the CR field to be tested is
-  the one that has just been modified by the operation.
-* When a 3-bit CR Result field is used the `inv CRbit` variant
-  must be used in order to select which CR Field bit shall
+  the one that has just been modified (created) by the operation.
+* When a 3-bit CR Result field is used the 3-bit variant
+  must be used, providing as it does the missing `CRbit`
+  in order to select which CR Field bit of the result shall
   be tested (EQ, LE, GE, SO)
 
 The reason why the 3-bit CR variant needs the additional CR-bit