From: Andreas Krebbel Date: Tue, 19 May 2015 17:32:07 +0000 (+0000) Subject: S/390 zvector builtin support. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3af82a61fa223fad00f5396b8f0ebb93cde646d1;p=gcc.git S/390 zvector builtin support. With this patch GCC implements an Altivec style set of builtins to make use of vector instructions in C/C++ code. This is provided for compatibility with the IBM XL compiler. gcc/ * config.gcc: Add vecintrin.h to extra_headers. Add s390-c.o to c_target_objs and cxx_target_objs. Add t-s390 to tmake_file. * config/s390/s390-builtin-types.def: New file. * config/s390/s390-builtins.def: New file. * config/s390/s390-builtins.h: New file. * config/s390/s390-c.c: New file. * config/s390/s390-modes.def: Add modes CCVEQANY, CCVH, CCVHANY, CCVHU, CCVHUANY, CCVFHANY, CCVFHEANY. * config/s390/s390-protos.h (s390_expand_vec_compare_cc) (s390_cpu_cpp_builtins, s390_register_target_pragmas): Add prototypes. * config/s390/s390.c (s390-builtins.h, s390-builtins.def): Include. (flags_builtin, flags_overloaded_builtin_var, s390_builtin_types) (s390_builtin_fn_types, s390_builtin_decls, code_for_builtin): New variable definitions. (s390_const_operand_ok): New function. (s390_expand_builtin): Rewrite. (s390_init_builtins): New function. (s390_handle_vectorbool_attribute): New function. (s390_attribute_table): Add s390_vector_bool attribute. (s390_match_ccmode_set): Handle new cc modes CCVH, CCVHU. (s390_branch_condition_mask): Generate masks for new modes. (s390_expand_vec_compare_cc): New function. (s390_mangle_type): Add mangling for vector bool types. (enum s390_builtin): Remove. (s390_atomic_assign_expand_fenv): Rename constants for sfpc and efpc builtins. * config/s390/s390.h (TARGET_CPU_CPP_BUILTINS): Call s390_cpu_cpp_builtins. (REGISTER_TARGET_PRAGMAS): New macro. * config/s390/s390.md: Define more UNSPEC_VEC_* constants. (insn_cmp mode attribute): Add new CC modes. (s390_sfpc, s390_efpc): Rename patterns to sfpc and efpc. (lcbb): New pattern definition. * config/s390/s390intrin.h: Include vecintrin.h. * config/s390/t-s390: New file. * config/s390/vecintrin.h: New file. * config/s390/vector.md: Include vx-builtins.md. * config/s390/vx-builtins.md: New file.S/390 zvector builtin support. From-SVN: r223398 --- diff --git a/gcc/config.gcc b/gcc/config.gcc index eb08a1d2f09..aa0c389cd4f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -457,7 +457,7 @@ spu*-*-*) s390*-*-*) cpu_type=s390 extra_options="${extra_options} fused-madd.opt" - extra_headers="s390intrin.h htmintrin.h htmxlintrin.h" + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" ;; # Note the 'l'; we need to be able to match e.g. "shle" or "shl". sh[123456789lbe]*-*-* | sh-*-*) @@ -2538,27 +2538,35 @@ rx-*-elf*) s390-*-linux*) default_gnu_indirect_function=yes tm_file="s390/s390.h dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h s390/linux.h" + c_target_objs="${c_target_objs} s390-c.o" + cxx_target_objs="${cxx_target_objs} s390-c.o" if test x$enable_targets = xall; then tmake_file="${tmake_file} s390/t-linux64" fi + tmake_file="${tmake_file} s390/t-s390" ;; s390x-*-linux*) default_gnu_indirect_function=yes tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h s390/linux.h" tm_p_file="linux-protos.h s390/s390-protos.h" + c_target_objs="${c_target_objs} s390-c.o" + cxx_target_objs="${cxx_target_objs} s390-c.o" md_file=s390/s390.md extra_modes=s390/s390-modes.def out_file=s390/s390.c - tmake_file="${tmake_file} s390/t-linux64" + tmake_file="${tmake_file} s390/t-linux64 s390/t-s390" ;; s390x-ibm-tpf*) - tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h s390/tpf.h" - tm_p_file=s390/s390-protos.h - md_file=s390/s390.md - extra_modes=s390/s390-modes.def - out_file=s390/s390.c - thread_file='tpf' + tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h s390/tpf.h" + tm_p_file=s390/s390-protos.h + c_target_objs="${c_target_objs} s390-c.o" + cxx_target_objs="${cxx_target_objs} s390-c.o" + md_file=s390/s390.md + extra_modes=s390/s390-modes.def + out_file=s390/s390.c + thread_file='tpf' extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" ;; sh-*-elf* | sh[12346l]*-*-elf* | \ sh-*-linux* | sh[2346lbe]*-*-linux* | \ diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def new file mode 100644 index 00000000000..8c65ae6f811 --- /dev/null +++ b/gcc/config/s390/s390-builtin-types.def @@ -0,0 +1,747 @@ +/* Builtin type definitions for IBM S/390 and zSeries + Copyright (C) 2015 Free Software Foundation, Inc. + + Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#define DEF_FN_TYPE_1(FN_TYPE, T1) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1]) +#define DEF_FN_TYPE_2(FN_TYPE, T1, T2) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1], \ + s390_builtin_types[T2]) +#define DEF_FN_TYPE_3(FN_TYPE, T1, T2, T3) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1], \ + s390_builtin_types[T2], \ + s390_builtin_types[T3]) +#define DEF_FN_TYPE_4(FN_TYPE, T1, T2, T3, T4) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1], \ + s390_builtin_types[T2], \ + s390_builtin_types[T3], \ + s390_builtin_types[T4]) +#define DEF_FN_TYPE_5(FN_TYPE, T1, T2, T3, T4, T5) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1], \ + s390_builtin_types[T2], \ + s390_builtin_types[T3], \ + s390_builtin_types[T4], \ + s390_builtin_types[T5]) +#define DEF_FN_TYPE_6(FN_TYPE, T1, T2, T3, T4, T5, T6) \ + DEF_FN_TYPE (FN_TYPE, \ + s390_builtin_types[T1], \ + s390_builtin_types[T2], \ + s390_builtin_types[T3], \ + s390_builtin_types[T4], \ + s390_builtin_types[T5], \ + s390_builtin_types[T6]) + +DEF_TYPE (BT_DBL, double_type_node, 0) +DEF_TYPE (BT_DBLCONST, double_type_node, 1) +DEF_TYPE (BT_FLTCONST, float_type_node, 1) +DEF_TYPE (BT_FLT, float_type_node, 0) +DEF_TYPE (BT_INTCONST, integer_type_node, 1) +DEF_TYPE (BT_INT, integer_type_node, 0) +DEF_TYPE (BT_LONG, long_integer_type_node, 0) +DEF_TYPE (BT_LONGLONGCONST, long_long_integer_type_node, 1) +DEF_TYPE (BT_LONGLONG, long_long_integer_type_node, 0) +DEF_TYPE (BT_UCHAR, unsigned_char_type_node, 0) +DEF_TYPE (BT_SCHAR, signed_char_type_node, 0) +DEF_TYPE (BT_SCHARCONST, signed_char_type_node, 1) +DEF_TYPE (BT_SHORTCONST, short_integer_type_node, 1) +DEF_TYPE (BT_SHORT, short_integer_type_node, 0) +DEF_TYPE (BT_UINT64, c_uint64_type_node, 0) +DEF_TYPE (BT_UINT, unsigned_type_node, 0) +DEF_TYPE (BT_UCHARCONST, unsigned_char_type_node, 1) +DEF_TYPE (BT_UINTCONST, unsigned_type_node, 1) +DEF_TYPE (BT_ULONGLONGCONST, long_long_unsigned_type_node, 1) +DEF_TYPE (BT_USHORTCONST, short_unsigned_type_node, 1) +DEF_TYPE (BT_VOIDCONST, void_type_node, 1) +DEF_TYPE (BT_VOID, void_type_node, 0) +DEF_TYPE (BT_ULONG, long_unsigned_type_node, 0) +DEF_TYPE (BT_ULONGLONG, long_long_unsigned_type_node, 0) +DEF_TYPE (BT_USHORT, short_unsigned_type_node, 0) +DEF_DISTINCT_TYPE (BT_BCHAR, BT_UCHAR) +DEF_DISTINCT_TYPE (BT_BINT, BT_UINT) +DEF_DISTINCT_TYPE (BT_BLONGLONG, BT_ULONGLONG) +DEF_DISTINCT_TYPE (BT_BSHORT, BT_USHORT) +DEF_POINTER_TYPE (BT_DBLPTR, BT_DBL) +DEF_POINTER_TYPE (BT_DBLCONSTPTR, BT_DBLCONST) +DEF_POINTER_TYPE (BT_FLTPTR, BT_FLT) +DEF_POINTER_TYPE (BT_FLTCONSTPTR, BT_FLTCONST) +DEF_POINTER_TYPE (BT_INTCONSTPTR, BT_INTCONST) +DEF_POINTER_TYPE (BT_INTPTR, BT_INT) +DEF_POINTER_TYPE (BT_LONGLONGCONSTPTR, BT_LONGLONGCONST) +DEF_POINTER_TYPE (BT_LONGLONGPTR, BT_LONGLONG) +DEF_POINTER_TYPE (BT_SCHARCONSTPTR, BT_SCHARCONST) +DEF_POINTER_TYPE (BT_SCHARPTR, BT_SCHAR) +DEF_POINTER_TYPE (BT_SHORTPTR, BT_SHORT) +DEF_POINTER_TYPE (BT_SHORTCONSTPTR, BT_SHORTCONST) +DEF_POINTER_TYPE (BT_UCHARPTR, BT_UCHAR) +DEF_POINTER_TYPE (BT_UCHARCONSTPTR, BT_UCHARCONST) +DEF_POINTER_TYPE (BT_UINTPTR, BT_UINT) +DEF_POINTER_TYPE (BT_UINTCONSTPTR, BT_UINTCONST) +DEF_POINTER_TYPE (BT_UINT64PTR, BT_UINT64) +DEF_POINTER_TYPE (BT_ULONGLONGPTR, BT_ULONGLONG) +DEF_POINTER_TYPE (BT_ULONGLONGCONSTPTR, BT_ULONGLONGCONST) +DEF_POINTER_TYPE (BT_USHORTCONSTPTR, BT_USHORTCONST) +DEF_POINTER_TYPE (BT_USHORTPTR, BT_USHORT) +DEF_POINTER_TYPE (BT_VOIDPTR, BT_VOID) +DEF_POINTER_TYPE (BT_VOIDCONSTPTR, BT_VOIDCONST) +DEF_VECTOR_TYPE (BT_V16QI, BT_SCHAR, 16) +DEF_VECTOR_TYPE (BT_V2DF, BT_DBL, 2) +DEF_VECTOR_TYPE (BT_V2DI, BT_LONGLONG, 2) +DEF_VECTOR_TYPE (BT_V4SI, BT_INT, 4) +DEF_VECTOR_TYPE (BT_V8HI, BT_SHORT, 8) +DEF_VECTOR_TYPE (BT_UV16QI, BT_UCHAR, 16) +DEF_VECTOR_TYPE (BT_UV2DI, BT_ULONGLONG, 2) +DEF_VECTOR_TYPE (BT_UV4SI, BT_UINT, 4) +DEF_VECTOR_TYPE (BT_UV8HI, BT_USHORT, 8) +DEF_OPAQUE_VECTOR_TYPE (BT_OV2DI, BT_LONGLONG, 2) +DEF_OPAQUE_VECTOR_TYPE (BT_OV4SI, BT_INT, 4) +DEF_OPAQUE_VECTOR_TYPE (BT_OUV4SI, BT_UINT, 4) +DEF_OPAQUE_VECTOR_TYPE (BT_BV16QI, BT_BCHAR, 16) +DEF_OPAQUE_VECTOR_TYPE (BT_BV2DI, BT_BLONGLONG, 2) +DEF_OPAQUE_VECTOR_TYPE (BT_BV4SI, BT_BINT, 4) +DEF_OPAQUE_VECTOR_TYPE (BT_BV8HI, BT_BSHORT, 8) +DEF_FN_TYPE_1 (BT_FN_UINT, BT_UINT) +DEF_FN_TYPE_1 (BT_FN_INT, BT_INT) +DEF_FN_TYPE_2 (BT_FN_VOID_UINT, BT_VOID, BT_UINT) +DEF_FN_TYPE_2 (BT_FN_VOID_INT, BT_VOID, BT_INT) +DEF_FN_TYPE_2 (BT_FN_INT_INT, BT_INT, BT_INT) +DEF_FN_TYPE_2 (BT_FN_INT_VOIDPTR, BT_INT, BT_VOIDPTR) +DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHARCONSTPTR, BT_UV16QI, BT_UCHARCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_UV16QI_USHORT, BT_UV16QI, BT_USHORT) +DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR, BT_UV16QI, BT_UCHAR) +DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_2 (BT_FN_UV2DI_ULONGLONG, BT_UV2DI, BT_ULONGLONG) +DEF_FN_TYPE_2 (BT_FN_UV2DI_ULONGLONGCONSTPTR, BT_UV2DI, BT_ULONGLONGCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_2 (BT_FN_UV2DI_UV4SI, BT_UV2DI, BT_UV4SI) +DEF_FN_TYPE_2 (BT_FN_OV4SI_INTCONSTPTR, BT_OV4SI, BT_INTCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_2 (BT_FN_OV4SI_INT, BT_OV4SI, BT_INT) +DEF_FN_TYPE_2 (BT_FN_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI) +DEF_FN_TYPE_2 (BT_FN_UV4SI_UINTCONSTPTR, BT_UV4SI, BT_UINTCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_UV4SI_UV8HI, BT_UV4SI, BT_UV8HI) +DEF_FN_TYPE_2 (BT_FN_UV4SI_UINT, BT_UV4SI, BT_UINT) +DEF_FN_TYPE_2 (BT_FN_UV8HI_USHORT, BT_UV8HI, BT_USHORT) +DEF_FN_TYPE_2 (BT_FN_UV8HI_UV16QI, BT_UV8HI, BT_UV16QI) +DEF_FN_TYPE_2 (BT_FN_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_2 (BT_FN_UV8HI_USHORTCONSTPTR, BT_UV8HI, BT_USHORTCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_V16QI_UCHAR, BT_V16QI, BT_UCHAR) +DEF_FN_TYPE_2 (BT_FN_V16QI_V16QI, BT_V16QI, BT_V16QI) +DEF_FN_TYPE_2 (BT_FN_V2DI_V16QI, BT_V2DI, BT_V16QI) +DEF_FN_TYPE_2 (BT_FN_V2DI_V2DI, BT_V2DI, BT_V2DI) +DEF_FN_TYPE_2 (BT_FN_V2DI_SHORT, BT_V2DI, BT_SHORT) +DEF_FN_TYPE_2 (BT_FN_V2DF_V2DF, BT_V2DF, BT_V2DF) +DEF_FN_TYPE_2 (BT_FN_V2DI_V8HI, BT_V2DI, BT_V8HI) +DEF_FN_TYPE_2 (BT_FN_V2DF_FLTCONSTPTR, BT_V2DF, BT_FLTCONSTPTR) +DEF_FN_TYPE_2 (BT_FN_V2DI_V4SI, BT_V2DI, BT_V4SI) +DEF_FN_TYPE_2 (BT_FN_V2DF_DBL, BT_V2DF, BT_DBL) +DEF_FN_TYPE_2 (BT_FN_V4SI_V8HI, BT_V4SI, BT_V8HI) +DEF_FN_TYPE_2 (BT_FN_V4SI_V4SI, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_2 (BT_FN_V4SI_SHORT, BT_V4SI, BT_SHORT) +DEF_FN_TYPE_2 (BT_FN_V8HI_V16QI, BT_V8HI, BT_V16QI) +DEF_FN_TYPE_2 (BT_FN_V8HI_V8HI, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_2 (BT_FN_V8HI_SHORT, BT_V8HI, BT_SHORT) +DEF_FN_TYPE_3 (BT_FN_INT_V2DI_V2DI, BT_INT, BT_V2DI, BT_V2DI) +DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_OV4SI, BT_INT, BT_OV4SI, BT_OV4SI) +DEF_FN_TYPE_3 (BT_FN_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF) +DEF_FN_TYPE_3 (BT_FN_USHORT_UV8HI_INT, BT_USHORT, BT_UV8HI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_INT_UV2DI_UV2DI, BT_INT, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_3 (BT_FN_ULONGLONG_UV2DI_INT, BT_ULONGLONG, BT_UV2DI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_INT_UV4SI_UV4SI, BT_INT, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_UCHAR_UV16QI_INT, BT_UCHAR, BT_UV16QI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_INT_UV8HI_UV8HI, BT_INT, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_INT_V4SI_V4SI, BT_INT, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_3 (BT_FN_INT_UV16QI_UV16QI, BT_INT, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_3 (BT_FN_INT_V16QI_V16QI, BT_INT, BT_V16QI, BT_V16QI) +DEF_FN_TYPE_3 (BT_FN_INT_VOIDPTR_INT, BT_INT, BT_VOIDPTR, BT_INT) +DEF_FN_TYPE_3 (BT_FN_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT) +DEF_FN_TYPE_3 (BT_FN_VOID_UINT64PTR_UINT64, BT_VOID, BT_UINT64PTR, BT_UINT64) +DEF_FN_TYPE_3 (BT_FN_INT_V8HI_V8HI, BT_INT, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_3 (BT_FN_UINT_VOIDCONSTPTR_INT, BT_UINT, BT_VOIDCONSTPTR, BT_INT) +DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_INT, BT_INT, BT_OV4SI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_VOID_V2DF_FLTPTR, BT_VOID, BT_V2DF, BT_FLTPTR) +DEF_FN_TYPE_3 (BT_FN_UINT_UV4SI_INT, BT_UINT, BT_UV4SI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI, BT_UV16QI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UCHARCONSTPTR_USHORT, BT_UV16QI, BT_UCHARCONSTPTR, BT_USHORT) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV4SI_UV4SI, BT_UV16QI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UCHAR_UCHAR, BT_UV16QI, BT_UCHAR, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UCHAR_INT, BT_UV16QI, BT_UCHAR, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV2DI_UV2DI, BT_UV16QI, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UINT, BT_UV16QI, BT_UV16QI, BT_UINT) +DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_FN_TYPE_3 (BT_FN_UV2DI_V2DF_INT, BT_UV2DI, BT_V2DF, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UINT, BT_UV2DI, BT_UV2DI, BT_UINT) +DEF_FN_TYPE_3 (BT_FN_OV2DI_LONGLONG_LONGLONG, BT_OV2DI, BT_LONGLONG, BT_LONGLONG) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_ULONGLONG, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UV8HI_UV8HI, BT_UV2DI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UCHAR_UCHAR, BT_UV2DI, BT_UCHAR, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV2DI_UV4SI_UV4SI, BT_UV2DI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_OV4SI_INT_INT, BT_OV4SI, BT_INT, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UINT_INT, BT_UV4SI, BT_UINT, BT_INT) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV8HI_UV8HI, BT_UV4SI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UINT, BT_UV4SI, BT_UV4SI, BT_UINT) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV16QI_UV16QI, BT_UV4SI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_3 (BT_FN_OV4SI_INTCONSTPTR_INT, BT_OV4SI, BT_INTCONSTPTR, BT_INT) +DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_INTPTR) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV2DI_UV2DI, BT_UV4SI, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_3 (BT_FN_OV4SI_INTCONSTPTR_UINT, BT_OV4SI, BT_INTCONSTPTR, BT_UINT) +DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_ULONG, BT_OV4SI, BT_OV4SI, BT_ULONG) +DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UCHAR_UCHAR, BT_UV4SI, BT_UCHAR, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV4SI_UV4SI, BT_UV8HI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV16QI_UV16QI, BT_UV8HI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UCHAR_UCHAR, BT_UV8HI, BT_UCHAR, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UINT, BT_UV8HI, BT_UV8HI, BT_UINT) +DEF_FN_TYPE_3 (BT_FN_UV8HI_USHORT_INT, BT_UV8HI, BT_USHORT, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V16QI_UV16QI_UV16QI, BT_V16QI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_3 (BT_FN_V16QI_UINT_VOIDCONSTPTR, BT_V16QI, BT_UINT, BT_VOIDCONSTPTR) +DEF_FN_TYPE_3 (BT_FN_V16QI_V8HI_V8HI, BT_V16QI, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_3 (BT_FN_V16QI_BV16QI_V16QI, BT_V16QI, BT_BV16QI, BT_V16QI) +DEF_FN_TYPE_3 (BT_FN_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) +DEF_FN_TYPE_3 (BT_FN_V2DI_V2DF_INT, BT_V2DI, BT_V2DF, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V2DI_V2DF_V2DF, BT_V2DI, BT_V2DF, BT_V2DF) +DEF_FN_TYPE_3 (BT_FN_V2DI_V4SI_V4SI, BT_V2DI, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_3 (BT_FN_V2DI_UV2DI_UV2DI, BT_V2DI, BT_UV2DI, BT_UV2DI) +DEF_FN_TYPE_3 (BT_FN_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI) +DEF_FN_TYPE_3 (BT_FN_V2DF_V2DI_INT, BT_V2DF, BT_V2DI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V2DF_UV2DI_INT, BT_V2DF, BT_UV2DI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF) +DEF_FN_TYPE_3 (BT_FN_V2DF_DBL_INT, BT_V2DF, BT_DBL, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V2DI_BV2DI_V2DI, BT_V2DI, BT_BV2DI, BT_V2DI) +DEF_FN_TYPE_3 (BT_FN_V2DF_UV4SI_INT, BT_V2DF, BT_UV4SI, BT_INT) +DEF_FN_TYPE_3 (BT_FN_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_3 (BT_FN_V4SI_V8HI_V8HI, BT_V4SI, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_3 (BT_FN_V4SI_INT_VOIDPTR, BT_V4SI, BT_INT, BT_VOIDPTR) +DEF_FN_TYPE_3 (BT_FN_V4SI_V2DI_V2DI, BT_V4SI, BT_V2DI, BT_V2DI) +DEF_FN_TYPE_3 (BT_FN_V4SI_UV4SI_UV4SI, BT_V4SI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_3 (BT_FN_V4SI_BV4SI_V4SI, BT_V4SI, BT_BV4SI, BT_V4SI) +DEF_FN_TYPE_3 (BT_FN_V8HI_BV8HI_V8HI, BT_V8HI, BT_BV8HI, BT_V8HI) +DEF_FN_TYPE_3 (BT_FN_V8HI_V16QI_V16QI, BT_V8HI, BT_V16QI, BT_V16QI) +DEF_FN_TYPE_3 (BT_FN_V8HI_V4SI_V4SI, BT_V8HI, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_3 (BT_FN_V8HI_UV8HI_UV8HI, BT_V8HI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_3 (BT_FN_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_4 (BT_FN_VOID_OV4SI_VOIDPTR_UINT, BT_VOID, BT_OV4SI, BT_VOIDPTR, BT_UINT) +DEF_FN_TYPE_4 (BT_FN_INT_OV4SI_OV4SI_INTPTR, BT_INT, BT_OV4SI, BT_OV4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_VOID_V16QI_UINT_VOIDPTR, BT_VOID, BT_V16QI, BT_UINT, BT_VOIDPTR) +DEF_FN_TYPE_4 (BT_FN_VOID_OV4SI_INT_VOIDPTR, BT_VOID, BT_OV4SI, BT_INT, BT_VOIDPTR) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, BT_UV16QI, BT_UCHAR, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI, BT_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV16QI) +DEF_FN_TYPE_4 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV2DI_UV4SI_UV4SI_UV2DI, BT_UV2DI, BT_UV4SI, BT_UV4SI, BT_UV2DI) +DEF_FN_TYPE_4 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, BT_ULONGLONG, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV2DI_UV2DI_INTPTR, BT_UV4SI, BT_UV2DI, BT_UV2DI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV4SI_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_OV4SI_INT_OV4SI_INT, BT_OV4SI, BT_INT, BT_OV4SI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_ULONGLONG) +DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV8HI_UV8HI_UV4SI, BT_UV4SI, BT_UV8HI, BT_UV8HI, BT_UV4SI) +DEF_FN_TYPE_4 (BT_FN_UV4SI_UV4SI_UINT_INT, BT_UV4SI, BT_UV4SI, BT_UINT, BT_INT) +DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UCHAR) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV4SI_UV4SI_INTPTR, BT_UV8HI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV16QI_UV16QI_UV8HI, BT_UV8HI, BT_UV16QI, BT_UV16QI, BT_UV8HI) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_UV8HI_UV8HI_USHORT_INT, BT_UV8HI, BT_UV8HI, BT_USHORT, BT_INT) +DEF_FN_TYPE_4 (BT_FN_V16QI_V8HI_V8HI_INTPTR, BT_V16QI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V16QI_UV16QI_UV16QI_INTPTR, BT_V16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) +DEF_FN_TYPE_4 (BT_FN_V2DI_V2DF_INT_INTPTR, BT_V2DI, BT_V2DF, BT_INT, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V2DI_V2DI_V2DI_INTPTR, BT_V2DI, BT_V2DI, BT_V2DI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V2DF_V2DF_DBL_INT, BT_V2DF, BT_V2DF, BT_DBL, BT_INT) +DEF_FN_TYPE_4 (BT_FN_V2DF_V2DF_UCHAR_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR, BT_UCHAR) +DEF_FN_TYPE_4 (BT_FN_V2DI_V2DF_V2DF_INTPTR, BT_V2DI, BT_V2DF, BT_V2DF, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V2DI_V4SI_V4SI_V2DI, BT_V2DI, BT_V4SI, BT_V4SI, BT_V2DI) +DEF_FN_TYPE_4 (BT_FN_V2DF_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF, BT_V2DF) +DEF_FN_TYPE_4 (BT_FN_V2DI_UV2DI_UV2DI_INTPTR, BT_V2DI, BT_UV2DI, BT_UV2DI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V4SI_V8HI_V8HI_V4SI, BT_V4SI, BT_V8HI, BT_V8HI, BT_V4SI) +DEF_FN_TYPE_4 (BT_FN_V4SI_UV4SI_UV4SI_INTPTR, BT_V4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V4SI_V2DI_V2DI_INTPTR, BT_V4SI, BT_V2DI, BT_V2DI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V4SI_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_V4SI) +DEF_FN_TYPE_4 (BT_FN_V8HI_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_V8HI) +DEF_FN_TYPE_4 (BT_FN_V8HI_UV8HI_UV8HI_INTPTR, BT_V8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V8HI_V16QI_V16QI_V8HI, BT_V8HI, BT_V16QI, BT_V16QI, BT_V8HI) +DEF_FN_TYPE_4 (BT_FN_V8HI_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_FN_TYPE_4 (BT_FN_V8HI_V4SI_V4SI_INTPTR, BT_V8HI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_FN_TYPE_5 (BT_FN_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG, BT_VOID, BT_UV4SI, BT_UV4SI, BT_UINTPTR, BT_ULONGLONG) +DEF_FN_TYPE_5 (BT_FN_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG, BT_VOID, BT_UV2DI, BT_UV2DI, BT_ULONGLONGPTR, BT_ULONGLONG) +DEF_FN_TYPE_5 (BT_FN_VOID_V4SI_V4SI_INTPTR_ULONGLONG, BT_VOID, BT_V4SI, BT_V4SI, BT_INTPTR, BT_ULONGLONG) +DEF_FN_TYPE_5 (BT_FN_UV16QI_UV16QI_UV16QI_INT_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT, BT_INTPTR) +DEF_FN_TYPE_5 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT) +DEF_FN_TYPE_5 (BT_FN_UV2DI_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT) +DEF_FN_TYPE_5 (BT_FN_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR) +DEF_FN_TYPE_5 (BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT) +DEF_FN_TYPE_5 (BT_FN_UV4SI_UV4SI_UV4SI_INT_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT, BT_INTPTR) +DEF_FN_TYPE_5 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR) +DEF_FN_TYPE_5 (BT_FN_OV4SI_OV4SI_OUV4SI_INTCONSTPTR_UCHAR, BT_OV4SI, BT_OV4SI, BT_OUV4SI, BT_INTCONSTPTR, BT_UCHAR) +DEF_FN_TYPE_5 (BT_FN_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR) +DEF_FN_TYPE_5 (BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT) +DEF_FN_TYPE_5 (BT_FN_UV8HI_UV8HI_UV8HI_INT_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT, BT_INTPTR) +DEF_FN_TYPE_6 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT, BT_INTPTR) +DEF_FN_TYPE_6 (BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT, BT_INTPTR) +DEF_FN_TYPE_6 (BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UCHAR, BT_UV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV16QI_V16QI, BT_UV16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UCHARCONSTPTR, BT_UV16QI, BT_UCHARCONSTPTR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV2DI_BV4SI, BT_BV2DI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV2DI_V2DI, BT_UV2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV4SI, BT_UV2DI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG, BT_UV2DI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONGCONSTPTR, BT_UV2DI, BT_ULONGLONGCONSTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_V4SI, BT_UV4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_BV4SI_BV8HI, BT_BV4SI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV4SI_UINTCONSTPTR, BT_UV4SI, BT_UINTCONSTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UINT, BT_UV4SI, BT_UINT) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV8HI, BT_UV4SI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_USHORTCONSTPTR, BT_UV8HI, BT_USHORTCONSTPTR) +DEF_OV_TYPE (BT_OV_BV8HI_BV16QI, BT_BV8HI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_UV8HI_USHORT, BT_UV8HI, BT_USHORT) +DEF_OV_TYPE (BT_OV_UV8HI_V8HI, BT_UV8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV16QI, BT_UV8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V16QI_SCHAR, BT_V16QI, BT_SCHAR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V16QI_SCHARCONSTPTR, BT_V16QI, BT_SCHARCONSTPTR) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONG, BT_V2DI, BT_LONGLONG) +DEF_OV_TYPE (BT_OV_V2DI_V8HI, BT_V2DI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V2DI_V16QI, BT_V2DI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONGCONSTPTR, BT_V2DI, BT_LONGLONGCONSTPTR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_V2DI_V4SI, BT_V2DI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V2DF_DBL, BT_V2DF, BT_DBL) +DEF_OV_TYPE (BT_OV_V2DF_V2DF, BT_V2DF, BT_V2DF) +DEF_OV_TYPE (BT_OV_V2DF_DBLCONSTPTR, BT_V2DF, BT_DBLCONSTPTR) +DEF_OV_TYPE (BT_OV_V4SI_INTCONSTPTR, BT_V4SI, BT_INTCONSTPTR) +DEF_OV_TYPE (BT_OV_V4SI_INT, BT_V4SI, BT_INT) +DEF_OV_TYPE (BT_OV_V4SI_V8HI, BT_V4SI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V8HI_V16QI, BT_V8HI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V8HI_SHORTCONSTPTR, BT_V8HI, BT_SHORTCONSTPTR) +DEF_OV_TYPE (BT_OV_V8HI_V8HI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_SHORT, BT_V8HI, BT_SHORT) +DEF_OV_TYPE (BT_OV_INT_UV2DI_BV2DI, BT_INT, BT_UV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT) +DEF_OV_TYPE (BT_OV_INT_V8HI_UV8HI, BT_INT, BT_V8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_INT_BV8HI_BV8HI, BT_INT, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_INT_V4SI_UV4SI, BT_INT, BT_V4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UCHAR_UV16QI_INT, BT_UCHAR, BT_UV16QI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_V2DI_UV2DI, BT_INT, BT_V2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_SHORT_V8HI_INT, BT_SHORT, BT_V8HI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_BV8HI_V8HI, BT_INT, BT_BV8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_USHORT_BV8HI_INT, BT_USHORT, BT_BV8HI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_BV8HI_UV8HI, BT_INT, BT_BV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UINT_UV4SI_INT, BT_UINT, BT_UV4SI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_UV8HI_UV8HI, BT_INT, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_LONGLONG_V2DI_INT, BT_LONGLONG, BT_V2DI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_UV8HI_BV8HI, BT_INT, BT_UV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_ULONGLONG_BV2DI_INT, BT_ULONGLONG, BT_BV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_V4SI_V4SI, BT_INT, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_INT_V8HI_BV8HI, BT_INT, BT_V8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_INT_V4SI_BV4SI, BT_INT, BT_V4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_INT_UV16QI_BV16QI, BT_INT, BT_UV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_INT_V2DF_UV2DI, BT_INT, BT_V2DF, BT_UV2DI) +DEF_OV_TYPE (BT_OV_INT_BV16QI_UV16QI, BT_INT, BT_BV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_INT_BV4SI_BV4SI, BT_INT, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_INT_BV16QI_BV16QI, BT_INT, BT_BV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_INT_BV4SI_V4SI, BT_INT, BT_BV4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_INT_V16QI_UV16QI, BT_INT, BT_V16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_INT_V16QI_V16QI, BT_INT, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_UCHAR_BV16QI_INT, BT_UCHAR, BT_BV16QI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_BV4SI_UV4SI, BT_INT, BT_BV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_INT_V4SI_INT, BT_INT, BT_V4SI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_UV4SI_UV4SI, BT_INT, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_ULONGLONG_UV2DI_INT, BT_ULONGLONG, BT_UV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_UV4SI_BV4SI, BT_INT, BT_UV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_INT_V8HI_V8HI, BT_INT, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_INT_V2DI_V2DI, BT_INT, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_INT_BV16QI_V16QI, BT_INT, BT_BV16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_INT_V2DI_BV2DI, BT_INT, BT_V2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_SCHAR_V16QI_INT, BT_SCHAR, BT_V16QI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_BV2DI_BV2DI, BT_INT, BT_BV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_UINT_BV4SI_INT, BT_UINT, BT_BV4SI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_BV2DI_V2DI, BT_INT, BT_BV2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_INT_UV16QI_UV16QI, BT_INT, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_INT_BV2DI_UV2DI, BT_INT, BT_BV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_USHORT_UV8HI_INT, BT_USHORT, BT_UV8HI, BT_INT) +DEF_OV_TYPE (BT_OV_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF) +DEF_OV_TYPE (BT_OV_INT_V16QI_BV16QI, BT_INT, BT_V16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_INT_UV2DI_UV2DI, BT_INT, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_ULONG, BT_UV16QI, BT_UV16QI, BT_ULONG) +DEF_OV_TYPE (BT_OV_BV16QI_BV8HI_BV8HI, BT_BV16QI, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV16QI_UV2DI_UV2DI, BT_UV16QI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_BV16QI_BV16QI, BT_UV16QI, BT_BV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_V16QI_V16QI, BT_BV16QI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_BV16QI, BT_UV16QI, BT_UV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UCHARCONSTPTR_UINT, BT_UV16QI, BT_UCHARCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_UV16QI_BV16QI_UV16QI, BT_UV16QI, BT_BV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UCHARCONSTPTR_USHORT, BT_UV16QI, BT_UCHARCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_UV16QI_LONG_UCHARPTR, BT_UV16QI, BT_LONG, BT_UCHARPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UCHAR_INT, BT_UV16QI, BT_UCHAR, BT_INT) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_UV4SI, BT_BV16QI, BT_BV16QI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV16QI_UV8HI_UV8HI, BT_UV16QI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_UV8HI, BT_BV16QI, BT_BV16QI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_UCHAR, BT_BV16QI, BT_BV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_UV16QI, BT_BV16QI, BT_BV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_UV16QI_UV16QI, BT_BV16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_V16QI, BT_UV16QI, BT_UV16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV4SI, BT_UV16QI, BT_UV16QI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV8HI, BT_UV16QI, BT_UV16QI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV16QI_V8HI_V8HI, BT_UV16QI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UV4SI_UV4SI, BT_UV16QI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV4SI_UV4SI, BT_UV2DI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONGCONSTPTR_USHORT, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_UV2DI_LONG_ULONGLONGPTR, BT_UV2DI, BT_LONG, BT_ULONGLONGPTR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV8HI, BT_UV2DI, BT_UV2DI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_BV2DI, BT_UV2DI, BT_UV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG_ULONGLONG, BT_UV2DI, BT_ULONGLONG, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_V2DI, BT_UV2DI, BT_UV2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONGCONSTPTR_UINT, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV4SI, BT_BV2DI, BT_BV2DI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_BV2DI_V2DI_V2DI, BT_BV2DI, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV16QI, BT_BV2DI, BT_BV2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV2DI_UV2DI_UV2DI, BT_BV2DI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_ULONG, BT_UV2DI, BT_UV2DI, BT_ULONG) +DEF_OV_TYPE (BT_OV_BV2DI_V2DF_V2DF, BT_BV2DI, BT_V2DF, BT_V2DF) +DEF_OV_TYPE (BT_OV_UV2DI_UV8HI_UV8HI, BT_UV2DI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV8HI, BT_BV2DI, BT_BV2DI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV2DI_BV2DI_UV2DI, BT_UV2DI, BT_BV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UCHAR, BT_BV2DI, BT_BV2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV4SI, BT_UV2DI, BT_UV2DI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_ULONGLONG, BT_INT) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV8HI, BT_UV4SI, BT_UV4SI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV4SI_V2DI_V2DI, BT_UV4SI, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_UV8HI, BT_BV4SI, BT_BV4SI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_V4SI, BT_UV4SI, BT_UV4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV4SI_UINT_INT, BT_UV4SI, BT_UINT, BT_INT) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_INTPTR, BT_BV4SI, BT_BV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_ULONG, BT_UV4SI, BT_UV4SI, BT_ULONG) +DEF_OV_TYPE (BT_OV_BV4SI_BV2DI_BV2DI, BT_BV4SI, BT_BV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_UV4SI, BT_BV4SI, BT_BV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_BV4SI, BT_UV4SI, BT_UV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV2DI_UV2DI, BT_UV4SI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI, BT_BV4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV16QI, BT_UV4SI, BT_UV4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UINTCONSTPTR_USHORT, BT_UV4SI, BT_UINTCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_UV4SI_BV4SI_BV4SI, BT_UV4SI, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_UCHAR, BT_BV4SI, BT_BV4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV4SI_UV16QI_UV16QI, BT_UV4SI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV4SI_UV8HI_UV8HI, BT_UV4SI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV4SI_LONG_UINTPTR, BT_UV4SI, BT_LONG, BT_UINTPTR) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_UV16QI, BT_BV4SI, BT_BV4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV4SI_V4SI_V4SI, BT_BV4SI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UINTCONSTPTR_UINT, BT_UV4SI, BT_UINTCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_UV4SI_BV4SI_UV4SI, BT_UV4SI, BT_BV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_V4SI_V4SI, BT_UV8HI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_UV8HI_USHORTCONSTPTR_UINT, BT_UV8HI, BT_USHORTCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV4SI, BT_UV8HI, BT_UV8HI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_BV8HI_V8HI_V8HI, BT_BV8HI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_BV8HI_BV4SI_BV4SI, BT_BV8HI, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_V8HI, BT_UV8HI, BT_UV8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV4SI_UV4SI, BT_UV8HI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV8HI_USHORT_INT, BT_UV8HI, BT_USHORT, BT_INT) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_UV16QI, BT_BV8HI, BT_BV8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV8HI_UV8HI_UV8HI, BT_BV8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_USHORTCONSTPTR_USHORT, BT_UV8HI, BT_USHORTCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_UV8HI_LONG_USHORTPTR, BT_UV8HI, BT_LONG, BT_USHORTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_UCHAR, BT_BV8HI, BT_BV8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_INTPTR, BT_BV8HI, BT_BV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_UV8HI, BT_BV8HI, BT_BV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV16QI, BT_UV8HI, BT_UV8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_BV8HI, BT_UV8HI, BT_UV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_UV4SI, BT_BV8HI, BT_BV8HI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV8HI_BV8HI_BV8HI, BT_UV8HI, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV16QI_UV16QI, BT_UV8HI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV8HI_BV8HI_UV8HI, BT_UV8HI, BT_BV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_ULONG, BT_UV8HI, BT_UV8HI, BT_ULONG) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V16QI_BV16QI_V16QI, BT_V16QI, BT_BV16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UCHAR, BT_V16QI, BT_V16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_BV16QI, BT_V16QI, BT_V16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_V16QI_LONG_SCHARPTR, BT_V16QI, BT_LONG, BT_SCHARPTR) +DEF_OV_TYPE (BT_OV_V16QI_SCHARCONSTPTR_UINT, BT_V16QI, BT_SCHARCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UV8HI, BT_V16QI, BT_V16QI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UV16QI, BT_V16QI, BT_V16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UV4SI, BT_V16QI, BT_V16QI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_ULONG, BT_V16QI, BT_V16QI, BT_ULONG) +DEF_OV_TYPE (BT_OV_V16QI_SCHARCONSTPTR_USHORT, BT_V16QI, BT_SCHARCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_V16QI_SCHAR_INT, BT_V16QI, BT_SCHAR, BT_INT) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V16QI_V8HI_V8HI, BT_V16QI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V2DF_UV2DI_INT, BT_V2DF, BT_UV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UCHAR, BT_V2DI, BT_V2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV16QI, BT_V2DI, BT_V2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V2DF_DBLCONSTPTR_USHORT, BT_V2DF, BT_DBLCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_V2DF_BV2DI_V2DF, BT_V2DF, BT_BV2DI, BT_V2DF) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_BV2DI) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV8HI, BT_V2DI, BT_V2DI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V2DF_DBLCONSTPTR_UINT, BT_V2DF, BT_DBLCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_V2DF_DBL_INT, BT_V2DF, BT_DBL, BT_INT) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_UV2DI) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV4SI, BT_V2DI, BT_V2DI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DI, BT_V2DF, BT_V2DF, BT_V2DI) +DEF_OV_TYPE (BT_OV_V2DI_BV2DI_V2DI, BT_V2DI, BT_BV2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_V2DI_LONG_LONGLONGPTR, BT_V2DI, BT_LONG, BT_LONGLONGPTR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_V2DI_V4SI_V4SI, BT_V2DI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV2DI, BT_V2DI, BT_V2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_V2DF_V2DI_INT, BT_V2DF, BT_V2DI, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONG_INT, BT_V2DI, BT_LONGLONG, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONGCONSTPTR_UINT, BT_V2DI, BT_LONGLONGCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_BV2DI, BT_V2DI, BT_V2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_V2DF_LONG_DBLPTR, BT_V2DF, BT_LONG, BT_DBLPTR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_ULONG, BT_V2DI, BT_V2DI, BT_ULONG) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONG_LONGLONG, BT_V2DI, BT_LONGLONG, BT_LONGLONG) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONGCONSTPTR_USHORT, BT_V2DI, BT_LONGLONGCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF) +DEF_OV_TYPE (BT_OV_V4SI_INTCONSTPTR_USHORT, BT_V4SI, BT_INTCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_V4SI_V8HI_V8HI, BT_V4SI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_BV4SI, BT_V4SI, BT_V4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_V4SI_INTCONSTPTR_UINT, BT_V4SI, BT_INTCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_V4SI_BV4SI_V4SI, BT_V4SI, BT_BV4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV8HI, BT_V4SI, BT_V4SI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_ULONG, BT_V4SI, BT_V4SI, BT_ULONG) +DEF_OV_TYPE (BT_OV_V4SI_INT_INT, BT_V4SI, BT_INT, BT_INT) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV4SI, BT_V4SI, BT_V4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV16QI, BT_V4SI, BT_V4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V4SI_LONG_INTPTR, BT_V4SI, BT_LONG, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UCHAR, BT_V4SI, BT_V4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V4SI_V2DI_V2DI, BT_V4SI, BT_V2DI, BT_V2DI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UV8HI, BT_V8HI, BT_V8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_ULONG, BT_V8HI, BT_V8HI, BT_ULONG) +DEF_OV_TYPE (BT_OV_V8HI_LONG_SHORTPTR, BT_V8HI, BT_LONG, BT_SHORTPTR) +DEF_OV_TYPE (BT_OV_V8HI_V4SI_V4SI, BT_V8HI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UV16QI, BT_V8HI, BT_V8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V8HI_BV8HI_V8HI, BT_V8HI, BT_BV8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UV4SI, BT_V8HI, BT_V8HI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_BV8HI, BT_V8HI, BT_V8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_V8HI_SHORTCONSTPTR_UINT, BT_V8HI, BT_SHORTCONSTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_V8HI_SHORT_INT, BT_V8HI, BT_SHORT, BT_INT) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UCHAR, BT_V8HI, BT_V8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V8HI_SHORTCONSTPTR_USHORT, BT_V8HI, BT_SHORTCONSTPTR, BT_USHORT) +DEF_OV_TYPE (BT_OV_V8HI_V16QI_V16QI, BT_V8HI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_VOID_V2DF_DBLPTR_UINT, BT_VOID, BT_V2DF, BT_DBLPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_UV16QI_UCHARPTR_UINT, BT_VOID, BT_UV16QI, BT_UCHARPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_V4SI_INTPTR_UINT, BT_VOID, BT_V4SI, BT_INTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_UV4SI_LONG_UINTPTR, BT_VOID, BT_UV4SI, BT_LONG, BT_UINTPTR) +DEF_OV_TYPE (BT_OV_VOID_V4SI_LONG_INTPTR, BT_VOID, BT_V4SI, BT_LONG, BT_INTPTR) +DEF_OV_TYPE (BT_OV_VOID_V2DI_LONG_LONGLONGPTR, BT_VOID, BT_V2DI, BT_LONG, BT_LONGLONGPTR) +DEF_OV_TYPE (BT_OV_VOID_V8HI_SHORTPTR_UINT, BT_VOID, BT_V8HI, BT_SHORTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_V2DF_LONG_DBLPTR, BT_VOID, BT_V2DF, BT_LONG, BT_DBLPTR) +DEF_OV_TYPE (BT_OV_VOID_UV8HI_USHORTPTR_UINT, BT_VOID, BT_UV8HI, BT_USHORTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_UV2DI_ULONGLONGPTR_UINT, BT_VOID, BT_UV2DI, BT_ULONGLONGPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_UV16QI_LONG_UCHARPTR, BT_VOID, BT_UV16QI, BT_LONG, BT_UCHARPTR) +DEF_OV_TYPE (BT_OV_VOID_UV8HI_LONG_USHORTPTR, BT_VOID, BT_UV8HI, BT_LONG, BT_USHORTPTR) +DEF_OV_TYPE (BT_OV_VOID_UV4SI_UINTPTR_UINT, BT_VOID, BT_UV4SI, BT_UINTPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_V16QI_SCHARPTR_UINT, BT_VOID, BT_V16QI, BT_SCHARPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_VOID_V16QI_LONG_SCHARPTR, BT_VOID, BT_V16QI, BT_LONG, BT_SCHARPTR) +DEF_OV_TYPE (BT_OV_VOID_V8HI_LONG_SHORTPTR, BT_VOID, BT_V8HI, BT_LONG, BT_SHORTPTR) +DEF_OV_TYPE (BT_OV_VOID_UV2DI_LONG_ULONGLONGPTR, BT_VOID, BT_UV2DI, BT_LONG, BT_ULONGLONGPTR) +DEF_OV_TYPE (BT_OV_VOID_V2DI_LONGLONGPTR_UINT, BT_VOID, BT_V2DI, BT_LONGLONGPTR, BT_UINT) +DEF_OV_TYPE (BT_OV_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_UV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_UCHAR_UV16QI_INT, BT_UV16QI, BT_UCHAR, BT_UV16QI, BT_INT) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_UV16QI_UV16QI_UV16QI, BT_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV16QI_BV16QI_BV16QI_INTPTR, BT_UV16QI, BT_BV16QI, BT_BV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV16QI_UV16QI_UV16QI_INTPTR, BT_BV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV16QI_V16QI_V16QI_INTPTR, BT_BV16QI, BT_V16QI, BT_V16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV16QI_UCHAR_BV16QI_INT, BT_UV16QI, BT_UCHAR, BT_BV16QI, BT_INT) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG_UV2DI_INT, BT_UV2DI, BT_ULONGLONG, BT_UV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_INT, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV4SI_UV4SI_UV2DI, BT_UV2DI, BT_UV4SI, BT_UV4SI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_BV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_UV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_UV16QI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG_BV2DI_INT, BT_UV2DI, BT_ULONGLONG, BT_BV2DI, BT_INT) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV8HI_UV8HI_UV4SI, BT_UV4SI, BT_UV8HI, BT_UV8HI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_BV4SI_V4SI_V4SI_INTPTR, BT_BV4SI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_INTPTR, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UINT_UV4SI_INT, BT_UV4SI, BT_UINT, BT_UV4SI, BT_INT) +DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_INTPTR, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV2DI_UV2DI_INTPTR, BT_UV4SI, BT_UV2DI, BT_UV2DI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_BV4SI_BV4SI_INTPTR, BT_UV4SI, BT_BV4SI, BT_BV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV16QI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_UV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_UV4SI, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UINT_BV4SI_INT, BT_UV4SI, BT_UINT, BT_BV4SI, BT_INT) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_UV16QI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_BV8HI_UV8HI_UV8HI_UV8HI, BT_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_INTPTR, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_UV4SI_UV4SI_INTPTR, BT_UV8HI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_UV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV16QI_UV16QI_UV8HI, BT_UV8HI, BT_UV16QI, BT_UV16QI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV16QI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV8HI_USHORT_BV8HI_INT, BT_UV8HI, BT_USHORT, BT_BV8HI, BT_INT) +DEF_OV_TYPE (BT_OV_BV8HI_V8HI_V8HI_INTPTR, BT_BV8HI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT) +DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_UV16QI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV8HI_UV8HI_UV8HI_INTPTR, BT_BV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_BV8HI_BV8HI_INTPTR, BT_UV8HI, BT_BV8HI, BT_BV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_USHORT_UV8HI_INT, BT_UV8HI, BT_USHORT, BT_UV8HI, BT_INT) +DEF_OV_TYPE (BT_OV_V16QI_SCHAR_V16QI_INT, BT_V16QI, BT_SCHAR, BT_V16QI, BT_INT) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_BV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_BV16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V16QI_UV16QI_V16QI_V16QI, BT_V16QI, BT_UV16QI, BT_V16QI, BT_V16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_ULONGLONG, BT_V16QI, BT_V16QI, BT_V16QI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_V16QI_V8HI_V8HI_INTPTR, BT_V16QI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UV16QI_UCHAR, BT_V16QI, BT_V16QI, BT_UV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_UV16QI_UV16QI, BT_V16QI, BT_V16QI, BT_UV16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INT, BT_V16QI, BT_V16QI, BT_V16QI, BT_INT) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV2DI_UCHAR, BT_V2DI, BT_V2DI, BT_UV2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_INT, BT_V2DI, BT_V2DI, BT_V2DI, BT_INT) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_ULONGLONG, BT_V2DF, BT_V2DF, BT_V2DF, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV16QI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV2DI) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_ULONGLONG, BT_V2DI, BT_V2DI, BT_V2DI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_V2DF_DBL_V2DF_INT, BT_V2DF, BT_DBL, BT_V2DF, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_V4SI_V4SI_V2DI, BT_V2DI, BT_V4SI, BT_V4SI, BT_V2DI) +DEF_OV_TYPE (BT_OV_V2DI_LONGLONG_V2DI_INT, BT_V2DI, BT_LONGLONG, BT_V2DI, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_BV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_BV2DI) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_BV2DI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_BV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_BV4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV16QI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INT, BT_V4SI, BT_V4SI, BT_V4SI, BT_INT) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV4SI_UV4SI, BT_V4SI, BT_V4SI, BT_UV4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_ULONGLONG, BT_V4SI, BT_V4SI, BT_V4SI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV4SI_UCHAR, BT_V4SI, BT_V4SI, BT_UV4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V4SI_V8HI_V8HI_V4SI, BT_V4SI, BT_V8HI, BT_V8HI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V4SI_UV4SI_V4SI_V4SI, BT_V4SI, BT_UV4SI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_V4SI) +DEF_OV_TYPE (BT_OV_V4SI_V2DI_V2DI_INTPTR, BT_V4SI, BT_V2DI, BT_V2DI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV4SI) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V4SI_INT_V4SI_INT, BT_V4SI, BT_INT, BT_V4SI, BT_INT) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INT, BT_V8HI, BT_V8HI, BT_V8HI, BT_INT) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UV8HI_UCHAR, BT_V8HI, BT_V8HI, BT_UV8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_UV8HI_UV8HI, BT_V8HI, BT_V8HI, BT_UV8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V8HI_UV8HI_V8HI_V8HI, BT_V8HI, BT_UV8HI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_V16QI_V16QI_V8HI, BT_V8HI, BT_V16QI, BT_V16QI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_BV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_BV8HI) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_ULONGLONG, BT_V8HI, BT_V8HI, BT_V8HI, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_V8HI_SHORT_V8HI_INT, BT_V8HI, BT_SHORT, BT_V8HI, BT_INT) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_V8HI) +DEF_OV_TYPE (BT_OV_V8HI_V4SI_V4SI_INTPTR, BT_V8HI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV16QI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV16QI) +DEF_OV_TYPE (BT_OV_VOID_V2DF_UV2DI_DBLPTR_ULONGLONG, BT_VOID, BT_V2DF, BT_UV2DI, BT_DBLPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_V4SI_UV4SI_INTPTR_ULONGLONG, BT_VOID, BT_V4SI, BT_UV4SI, BT_INTPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG, BT_VOID, BT_UV2DI, BT_UV2DI, BT_ULONGLONGPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG, BT_VOID, BT_UV4SI, BT_UV4SI, BT_UINTPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_BV2DI_UV2DI_ULONGLONGPTR_ULONGLONG, BT_VOID, BT_BV2DI, BT_UV2DI, BT_ULONGLONGPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_V2DI_UV2DI_LONGLONGPTR_ULONGLONG, BT_VOID, BT_V2DI, BT_UV2DI, BT_LONGLONGPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_VOID_BV4SI_UV4SI_UINTPTR_ULONGLONG, BT_VOID, BT_BV4SI, BT_UV4SI, BT_UINTPTR, BT_ULONGLONG) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV16QI_UV16QI_UV16QI_UV16QI_INTPTR, BT_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_BV2DI, BT_BV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_BV4SI, BT_BV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_UV4SI_INTPTR, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_BV8HI_UV8HI_UV8HI_UV8HI_INTPTR, BT_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV2DI_LONGLONGCONSTPTR_UCHAR, BT_V2DI, BT_V2DI, BT_UV2DI, BT_LONGLONGCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR, BT_V2DF, BT_V2DF, BT_UV2DI, BT_DBLCONSTPTR, BT_UCHAR) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_UV4SI_INTCONSTPTR_UCHAR, BT_V4SI, BT_V4SI, BT_UV4SI, BT_INTCONSTPTR, BT_UCHAR) diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def new file mode 100644 index 00000000000..357be2aa9e2 --- /dev/null +++ b/gcc/config/s390/s390-builtins.def @@ -0,0 +1,2486 @@ +/* Builtin definitions for IBM S/390 and zSeries + Copyright (C) 2015 Free Software Foundation, Inc. + + Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#undef O_U1 +#undef O_U2 +#undef O_U3 +#undef O_U4 +#undef O_U5 +#undef O_U8 +#undef O_U12 +#undef O_U16 +#undef O_U32 + +#undef O_S2 +#undef O_S3 +#undef O_S4 +#undef O_S5 +#undef O_S8 +#undef O_S12 +#undef O_S16 +#undef O_S32 +#undef O_ELEM +#undef O_LIT + +#undef O1_U1 +#undef O2_U1 +#undef O3_U1 +#undef O4_U1 + +#undef O1_U2 +#undef O2_U2 +#undef O3_U2 +#undef O4_U2 + +#undef O1_U3 +#undef O2_U3 +#undef O3_U3 +#undef O4_U3 + +#undef O1_U4 +#undef O2_U4 +#undef O3_U4 +#undef O4_U4 + +#undef O1_U5 +#undef O2_U5 +#undef O3_U5 +#undef O4_U5 + +#undef O1_U8 +#undef O2_U8 +#undef O3_U8 +#undef O4_U8 + +#undef O1_U12 +#undef O2_U12 +#undef O3_U12 +#undef O4_U12 + +#undef O1_U16 +#undef O2_U16 +#undef O3_U16 +#undef O4_U16 + +#undef O1_U32 +#undef O2_U32 +#undef O3_U32 +#undef O4_U32 + +#undef O1_S2 +#undef O2_S2 +#undef O3_S2 +#undef O4_S2 + +#undef O1_S3 +#undef O2_S3 +#undef O3_S3 +#undef O4_S3 + +#undef O1_S4 +#undef O2_S4 +#undef O3_S4 +#undef O4_S4 + +#undef O1_S5 +#undef O2_S5 +#undef O3_S5 +#undef O4_S5 + +#undef O1_S8 +#undef O2_S8 +#undef O3_S8 +#undef O4_S8 + +#undef O1_S12 +#undef O2_S12 +#undef O3_S12 +#undef O4_S12 + +#undef O1_S16 +#undef O2_S16 +#undef O3_S16 +#undef O4_S16 + +#undef O1_S32 +#undef O2_S32 +#undef O3_S32 +#undef O4_S32 + +#undef O1_ELEM +#undef O2_ELEM +#undef O3_ELEM +#undef O4_ELEM + +#undef O1_LIT +#undef O2_LIT +#undef O3_LIT +#undef O4_LIT + +#undef O_SHIFT +#undef O_IMM_P +#undef O_UIMM_P +#undef O_SIMM_P + +#define O_U1 1 /* unsigned 1 bit literal */ +#define O_U2 2 /* unsigned 2 bit literal */ +#define O_U3 3 /* unsigned 3 bit literal */ +#define O_U4 4 /* unsigned 4 bit literal */ +#define O_U5 5 /* unsigned 5 bit literal */ +#define O_U8 6 /* unsigned 8 bit literal */ +#define O_U12 7 /* unsigned 16 bit literal */ +#define O_U16 8 /* unsigned 16 bit literal */ +#define O_U32 9 /* unsigned 32 bit literal */ + +#define O_S2 10 /* signed 2 bit literal */ +#define O_S3 11 /* signed 3 bit literal */ +#define O_S4 12 /* signed 4 bit literal */ +#define O_S5 13 /* signed 5 bit literal */ +#define O_S8 14 /* signed 8 bit literal */ +#define O_S12 15 /* signed 12 bit literal */ +#define O_S16 16 /* signed 16 bit literal */ +#define O_S32 17 /* signed 32 bit literal */ + +#define O_ELEM 18 /* Element selector requiring modulo arithmetic. */ +#define O_LIT 19 /* Operand must be a literal fitting the target type. */ + +#define O_SHIFT 5 + +#define O_UIMM_P(X) ((X) >= O_U1 && (X) <= O_U32) +#define O_SIMM_P(X) ((X) >= O_S2 && (X) <= O_S32) +#define O_IMM_P(X) ((X) == O_LIT || ((X) >= O_U1 && (X) <= O_S32)) + +#define O1_U1 O_U1 +#define O2_U1 (O_U1 << O_SHIFT) +#define O3_U1 (O_U1 << (2 * O_SHIFT)) +#define O4_U1 (O_U1 << (3 * O_SHIFT)) + +#define O1_U2 O_U2 +#define O2_U2 (O_U2 << O_SHIFT) +#define O3_U2 (O_U2 << (2 * O_SHIFT)) +#define O4_U2 (O_U2 << (3 * O_SHIFT)) + +#define O1_U3 O_U3 +#define O2_U3 (O_U3 << O_SHIFT) +#define O3_U3 (O_U3 << (2 * O_SHIFT)) +#define O4_U3 (O_U3 << (3 * O_SHIFT)) + +#define O1_U4 O_U4 +#define O2_U4 (O_U4 << O_SHIFT) +#define O3_U4 (O_U4 << (2 * O_SHIFT)) +#define O4_U4 (O_U4 << (3 * O_SHIFT)) + +#define O1_U5 O_U5 +#define O2_U5 (O_U5 << O_SHIFT) +#define O3_U5 (O_U5 << (2 * O_SHIFT)) +#define O4_U5 (O_U5 << (3 * O_SHIFT)) + +#define O1_U8 O_U8 +#define O2_U8 (O_U8 << O_SHIFT) +#define O3_U8 (O_U8 << (2 * O_SHIFT)) +#define O4_U8 (O_U8 << (3 * O_SHIFT)) + +#define O1_U12 O_U12 +#define O2_U12 (O_U12 << O_SHIFT) +#define O3_U12 (O_U12 << (2 * O_SHIFT)) +#define O4_U12 (O_U12 << (3 * O_SHIFT)) + +#define O1_U16 O_U16 +#define O2_U16 (O_U16 << O_SHIFT) +#define O3_U16 (O_U16 << (2 * O_SHIFT)) +#define O4_U16 (O_U16 << (3 * O_SHIFT)) + +#define O1_U32 O_U32 +#define O2_U32 (O_U32 << O_SHIFT) +#define O3_U32 (O_U32 << (2 * O_SHIFT)) +#define O4_U32 (O_U32 << (3 * O_SHIFT)) + + +#define O1_S2 O_S2 +#define O2_S2 (O_S2 << O_SHIFT) +#define O3_S2 (O_S2 << (2 * O_SHIFT)) +#define O4_S2 (O_S2 << (3 * O_SHIFT)) + +#define O1_S3 O_S3 +#define O2_S3 (O_S3 << O_SHIFT) +#define O3_S3 (O_S3 << (2 * O_SHIFT)) +#define O4_S3 (O_S3 << (3 * O_SHIFT)) + +#define O1_S4 O_S4 +#define O2_S4 (O_S4 << O_SHIFT) +#define O3_S4 (O_S4 << (2 * O_SHIFT)) +#define O4_S4 (O_S4 << (3 * O_SHIFT)) + +#define O1_S5 O_S5 +#define O2_S5 (O_S5 << O_SHIFT) +#define O3_S5 (O_S5 << (2 * O_SHIFT)) +#define O4_S5 (O_S5 << (3 * O_SHIFT)) + +#define O1_S8 O_S8 +#define O2_S8 (O_S8 << O_SHIFT) +#define O3_S8 (O_S8 << (2 * O_SHIFT)) +#define O4_S8 (O_S8 << (3 * O_SHIFT)) + +#define O1_S12 O_S12 +#define O2_S12 (O_S12 << O_SHIFT) +#define O3_S12 (O_S12 << (2 * O_SHIFT)) +#define O4_S12 (O_S12 << (3 * O_SHIFT)) + +#define O1_S16 O_S16 +#define O2_S16 (O_S16 << O_SHIFT) +#define O3_S16 (O_S16 << (2 * O_SHIFT)) +#define O4_S16 (O_S16 << (3 * O_SHIFT)) + +#define O1_S32 O_S32 +#define O2_S32 (O_S32 << O_SHIFT) +#define O3_S32 (O_S32 << (2 * O_SHIFT)) +#define O4_S32 (O_S32 << (3 * O_SHIFT)) + +#define O1_ELEM O_ELEM +#define O2_ELEM (O_ELEM << O_SHIFT) +#define O3_ELEM (O_ELEM << (2 * O_SHIFT)) +#define O4_ELEM (O_ELEM << (3 * O_SHIFT)) + +#define O1_LIT O_LIT +#define O2_LIT (O_LIT << O_SHIFT) +#define O3_LIT (O_LIT << (2 * O_SHIFT)) +#define O4_LIT (O_LIT << (3 * O_SHIFT)) + + +/* Builtin flags. Flags applying to the whole builtin definition. */ + +#undef B_INT + +#define B_INT (1 << (4 * O_SHIFT)) /* Internal builtins. This builtin cannot be used in user programs. */ + + +/* B_DEF defines a standard (not overloaded) builtin + B_DEF (, , , , ) + + OB_DEF defines an overloaded builtin + OB_DEF (, , , , ) + + OB_DEF_VAR defines a variant of an overloaded builtin + OB_DEF_VAR (, , , ) */ + + +B_DEF (tbeginc, tbeginc, 0, 0, BT_FN_INT) +B_DEF (tbegin, tbegin, returns_twice_attr, 0, BT_FN_INT_VOIDPTR) +B_DEF (tbegin_nofloat, tbegin_nofloat, returns_twice_attr, 0, BT_FN_INT_VOIDPTR) +B_DEF (tbegin_retry, tbegin_retry, returns_twice_attr, 0, BT_FN_INT_VOIDPTR_INT) +B_DEF (tbegin_retry_nofloat, tbegin_retry_nofloat,returns_twice_attr,0, BT_FN_INT_VOIDPTR_INT) +B_DEF (tend, tend, 0, 0, BT_FN_INT) +B_DEF (tabort, tabort, noreturn_attr, 0, BT_FN_VOID_INT) +B_DEF (tx_nesting_depth, etnd, 0, 0, BT_FN_INT) +B_DEF (non_tx_store, ntstg, 0, 0, BT_FN_VOID_UINT64PTR_UINT64) +B_DEF (tx_assist, tx_assist, 0, 0, BT_FN_VOID_INT) +B_DEF (s390_sfpc, sfpc, 0, 0, BT_FN_VOID_UINT) +B_DEF (s390_efpc, efpc, 0, 0, BT_FN_UINT) +B_DEF (s390_lcbb, lcbb, 0, O2_U4, BT_FN_UINT_VOIDCONSTPTR_INT) + +OB_DEF (s390_vec_step, MAX, MAX, BT_FN_INT_INT) + +OB_DEF (s390_vec_gather_element, s390_vec_gather_element_s32,s390_vec_gather_element_dbl,BT_FN_OV4SI_OV4SI_OUV4SI_INTCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_s32,s390_vgef, O4_U2, BT_OV_V4SI_V4SI_UV4SI_INTCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_b32,s390_vgef, O4_U2, BT_OV_BV4SI_BV4SI_UV4SI_UINTCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_u32,s390_vgef, O4_U2, BT_OV_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_s64,s390_vgeg, O4_U1, BT_OV_V2DI_V2DI_UV2DI_LONGLONGCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_b64,s390_vgeg, O4_U1, BT_OV_BV2DI_BV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_u64,s390_vgeg, O4_U1, BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR) +OB_DEF_VAR (s390_vec_gather_element_dbl,s390_vgeg, O4_U1, BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR) + +B_DEF (s390_vgef, vec_gather_elementv4si,0, O4_U2, BT_FN_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR) +B_DEF (s390_vgeg, vec_gather_elementv2di,0, O4_U1, BT_FN_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR) +B_DEF (s390_vgbm, vec_genbytemaskv16qi,0, O1_U16, BT_FN_UV16QI_USHORT) +B_DEF (s390_vgmb, vec_genmaskv16qi, 0, O1_U8 | O2_U8, BT_FN_UV16QI_UCHAR_UCHAR) +B_DEF (s390_vgmh, vec_genmaskv8hi, 0, O1_U8 | O2_U8, BT_FN_UV8HI_UCHAR_UCHAR) +B_DEF (s390_vgmf, vec_genmaskv4si, 0, O1_U8 | O2_U8, BT_FN_UV4SI_UCHAR_UCHAR) +B_DEF (s390_vgmg, vec_genmaskv2di, 0, O1_U8 | O2_U8, BT_FN_UV2DI_UCHAR_UCHAR) + +OB_DEF (s390_vec_xld2, s390_vec_xld2_s8, s390_vec_xld2_dbl, BT_FN_V4SI_INT_VOIDPTR) +OB_DEF_VAR (s390_vec_xld2_s8, MAX, O1_LIT, BT_OV_V16QI_LONG_SCHARPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_u8, MAX, O1_LIT, BT_OV_UV16QI_LONG_UCHARPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_s16, MAX, O1_LIT, BT_OV_V8HI_LONG_SHORTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_u16, MAX, O1_LIT, BT_OV_UV8HI_LONG_USHORTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_s32, MAX, O1_LIT, BT_OV_V4SI_LONG_INTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_u32, MAX, O1_LIT, BT_OV_UV4SI_LONG_UINTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_s64, MAX, O1_LIT, BT_OV_V2DI_LONG_LONGLONGPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_u64, MAX, O1_LIT, BT_OV_UV2DI_LONG_ULONGLONGPTR) /* vl */ +OB_DEF_VAR (s390_vec_xld2_dbl, MAX, O1_LIT, BT_OV_V2DF_LONG_DBLPTR) /* vl */ + +OB_DEF (s390_vec_xlw4, s390_vec_xlw4_s8, s390_vec_xlw4_u32, BT_FN_V4SI_INT_VOIDPTR) +OB_DEF_VAR (s390_vec_xlw4_s8, MAX, O1_LIT, BT_OV_V16QI_LONG_SCHARPTR) /* vl */ +OB_DEF_VAR (s390_vec_xlw4_u8, MAX, O1_LIT, BT_OV_UV16QI_LONG_UCHARPTR) /* vl */ +OB_DEF_VAR (s390_vec_xlw4_s16, MAX, O1_LIT, BT_OV_V8HI_LONG_SHORTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xlw4_u16, MAX, O1_LIT, BT_OV_UV8HI_LONG_USHORTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xlw4_s32, MAX, O1_LIT, BT_OV_V4SI_LONG_INTPTR) /* vl */ +OB_DEF_VAR (s390_vec_xlw4_u32, MAX, O1_LIT, BT_OV_UV4SI_LONG_UINTPTR) /* vl */ + +OB_DEF (s390_vec_splats, s390_vec_splats_s8, s390_vec_splats_dbl,BT_FN_OV4SI_INT) +OB_DEF_VAR (s390_vec_splats_s8, s390_vlrepb, 0, BT_OV_V16QI_SCHAR) +OB_DEF_VAR (s390_vec_splats_u8, s390_vlrepb, 0, BT_OV_UV16QI_UCHAR) +OB_DEF_VAR (s390_vec_splats_s16, s390_vlreph, 0, BT_OV_V8HI_SHORT) +OB_DEF_VAR (s390_vec_splats_u16, s390_vlreph, 0, BT_OV_UV8HI_USHORT) +OB_DEF_VAR (s390_vec_splats_s32, s390_vlrepf, 0, BT_OV_V4SI_INT) +OB_DEF_VAR (s390_vec_splats_u32, s390_vlrepf, 0, BT_OV_UV4SI_UINT) +OB_DEF_VAR (s390_vec_splats_s64, s390_vlrepg, 0, BT_OV_V2DI_LONGLONG) +OB_DEF_VAR (s390_vec_splats_u64, s390_vlrepg, 0, BT_OV_UV2DI_ULONGLONG) +OB_DEF_VAR (s390_vec_splats_dbl, s390_vlrepg_dbl, 0, BT_OV_V2DF_DBL) /* vlrepg */ + +B_DEF (s390_vlrepb, vec_splatsv16qi, 0, 0, BT_FN_UV16QI_UCHAR) +B_DEF (s390_vlreph, vec_splatsv8hi, 0, 0, BT_FN_UV8HI_USHORT) +B_DEF (s390_vlrepf, vec_splatsv4si, 0, 0, BT_FN_UV4SI_UINT) +B_DEF (s390_vlrepg, vec_splatsv2di, 0, 0, BT_FN_UV2DI_ULONGLONG) +B_DEF (s390_vlrepg_dbl, vec_splatsv2df, 0, B_INT, BT_FN_V2DF_DBL) +B_DEF (s390_vrepib, vec_splatsv16qi, 0, O1_U8, BT_FN_V16QI_UCHAR) +B_DEF (s390_vrepih, vec_splatsv8hi, 0, O1_S16, BT_FN_V8HI_SHORT) +B_DEF (s390_vrepif, vec_splatsv4si, 0, O1_S16, BT_FN_V4SI_SHORT) +B_DEF (s390_vrepig, vec_splatsv2di, 0, O1_S16, BT_FN_V2DI_SHORT) + +OB_DEF (s390_vec_insert, s390_vec_insert_s8, s390_vec_insert_dbl,BT_FN_OV4SI_INT_OV4SI_INT) +OB_DEF_VAR (s390_vec_insert_s8, s390_vlvgb, O3_ELEM, BT_OV_V16QI_SCHAR_V16QI_INT) +OB_DEF_VAR (s390_vec_insert_u8, s390_vlvgb, O3_ELEM, BT_OV_UV16QI_UCHAR_UV16QI_INT) +OB_DEF_VAR (s390_vec_insert_b8, s390_vlvgb, O3_ELEM, BT_OV_UV16QI_UCHAR_BV16QI_INT) +OB_DEF_VAR (s390_vec_insert_s16, s390_vlvgh, O3_ELEM, BT_OV_V8HI_SHORT_V8HI_INT) +OB_DEF_VAR (s390_vec_insert_u16, s390_vlvgh, O3_ELEM, BT_OV_UV8HI_USHORT_UV8HI_INT) +OB_DEF_VAR (s390_vec_insert_b16, s390_vlvgh, O3_ELEM, BT_OV_UV8HI_USHORT_BV8HI_INT) +OB_DEF_VAR (s390_vec_insert_s32, s390_vlvgf, O3_ELEM, BT_OV_V4SI_INT_V4SI_INT) +OB_DEF_VAR (s390_vec_insert_u32, s390_vlvgf, O3_ELEM, BT_OV_UV4SI_UINT_UV4SI_INT) +OB_DEF_VAR (s390_vec_insert_b32, s390_vlvgf, O3_ELEM, BT_OV_UV4SI_UINT_BV4SI_INT) +OB_DEF_VAR (s390_vec_insert_s64, s390_vlvgg, O3_ELEM, BT_OV_V2DI_LONGLONG_V2DI_INT) +OB_DEF_VAR (s390_vec_insert_u64, s390_vlvgg, O3_ELEM, BT_OV_UV2DI_ULONGLONG_UV2DI_INT) +OB_DEF_VAR (s390_vec_insert_b64, s390_vlvgg, O3_ELEM, BT_OV_UV2DI_ULONGLONG_BV2DI_INT) +OB_DEF_VAR (s390_vec_insert_dbl, s390_vlvgg_dbl, O3_ELEM, BT_OV_V2DF_DBL_V2DF_INT) + +B_DEF (s390_vlvgb, vec_insertv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UCHAR_INT) +B_DEF (s390_vlvgh, vec_insertv8hi, 0, 0, BT_FN_UV8HI_UV8HI_USHORT_INT) +B_DEF (s390_vlvgf, vec_insertv4si, 0, 0, BT_FN_UV4SI_UV4SI_UINT_INT) +B_DEF (s390_vlvgg, vec_insertv2di, 0, 0, BT_FN_UV2DI_UV2DI_ULONGLONG_INT) +B_DEF (s390_vlvgg_dbl, vec_insertv2df, 0, B_INT, BT_FN_V2DF_V2DF_DBL_INT) + +OB_DEF (s390_vec_promote, s390_vec_promote_s8,s390_vec_promote_dbl,BT_FN_OV4SI_INT_INT) +OB_DEF_VAR (s390_vec_promote_s8, s390_vlvgb_noin, O2_ELEM, BT_OV_V16QI_SCHAR_INT) /* vlvgb */ +OB_DEF_VAR (s390_vec_promote_u8, s390_vlvgb_noin, O2_ELEM, BT_OV_UV16QI_UCHAR_INT) /* vlvgb */ +OB_DEF_VAR (s390_vec_promote_s16, s390_vlvgh_noin, O2_ELEM, BT_OV_V8HI_SHORT_INT) /* vlvgh */ +OB_DEF_VAR (s390_vec_promote_u16, s390_vlvgh_noin, O2_ELEM, BT_OV_UV8HI_USHORT_INT) /* vlvgh */ +OB_DEF_VAR (s390_vec_promote_s32, s390_vlvgf_noin, O2_ELEM, BT_OV_V4SI_INT_INT) /* vlvgf */ +OB_DEF_VAR (s390_vec_promote_u32, s390_vlvgf_noin, O2_ELEM, BT_OV_UV4SI_UINT_INT) /* vlvgf */ +OB_DEF_VAR (s390_vec_promote_s64, s390_vlvgg_noin, O2_ELEM, BT_OV_V2DI_LONGLONG_INT) /* vlvgg */ +OB_DEF_VAR (s390_vec_promote_u64, s390_vlvgg_noin, O2_ELEM, BT_OV_UV2DI_ULONGLONG_INT) /* vlvgg */ +OB_DEF_VAR (s390_vec_promote_dbl, s390_vlvgg_dbl_noin,O2_ELEM, BT_OV_V2DF_DBL_INT) /* vlvgg */ + +B_DEF (s390_vlvgb_noin, vec_promotev16qi, 0, B_INT, BT_FN_UV16QI_UCHAR_INT) +B_DEF (s390_vlvgh_noin, vec_promotev8hi, 0, B_INT, BT_FN_UV8HI_USHORT_INT) +B_DEF (s390_vlvgf_noin, vec_promotev4si, 0, B_INT, BT_FN_UV4SI_UINT_INT) +B_DEF (s390_vlvgg_noin, vec_promotev2di, 0, B_INT, BT_FN_UV2DI_ULONGLONG_INT) +B_DEF (s390_vlvgg_dbl_noin, vec_promotev2df, 0, B_INT, BT_FN_V2DF_DBL_INT) + +OB_DEF (s390_vec_extract, s390_vec_extract_s8,s390_vec_extract_dbl,BT_FN_INT_OV4SI_INT) +OB_DEF_VAR (s390_vec_extract_s8, s390_vlgvb, O2_ELEM, BT_OV_SCHAR_V16QI_INT) +OB_DEF_VAR (s390_vec_extract_u8, s390_vlgvb, O2_ELEM, BT_OV_UCHAR_UV16QI_INT) +OB_DEF_VAR (s390_vec_extract_b8, s390_vlgvb, O2_ELEM, BT_OV_UCHAR_BV16QI_INT) +OB_DEF_VAR (s390_vec_extract_s16, s390_vlgvh, O2_ELEM, BT_OV_SHORT_V8HI_INT) +OB_DEF_VAR (s390_vec_extract_u16, s390_vlgvh, O2_ELEM, BT_OV_USHORT_UV8HI_INT) +OB_DEF_VAR (s390_vec_extract_b16, s390_vlgvh, O2_ELEM, BT_OV_USHORT_BV8HI_INT) +OB_DEF_VAR (s390_vec_extract_s32, s390_vlgvf, O2_ELEM, BT_OV_INT_V4SI_INT) +OB_DEF_VAR (s390_vec_extract_u32, s390_vlgvf, O2_ELEM, BT_OV_UINT_UV4SI_INT) +OB_DEF_VAR (s390_vec_extract_b32, s390_vlgvf, O2_ELEM, BT_OV_UINT_BV4SI_INT) +OB_DEF_VAR (s390_vec_extract_s64, s390_vlgvg, O2_ELEM, BT_OV_LONGLONG_V2DI_INT) +OB_DEF_VAR (s390_vec_extract_u64, s390_vlgvg, O2_ELEM, BT_OV_ULONGLONG_UV2DI_INT) +OB_DEF_VAR (s390_vec_extract_b64, s390_vlgvg, O2_ELEM, BT_OV_ULONGLONG_BV2DI_INT) +OB_DEF_VAR (s390_vec_extract_dbl, s390_vlgvg_dbl, O2_ELEM, BT_OV_DBL_V2DF_INT) /* vlgvg */ + +B_DEF (s390_vlgvb, vec_extractv16qi, 0, 0, BT_FN_UCHAR_UV16QI_INT) +B_DEF (s390_vlgvh, vec_extractv8hi, 0, 0, BT_FN_USHORT_UV8HI_INT) +B_DEF (s390_vlgvf, vec_extractv4si, 0, 0, BT_FN_UINT_UV4SI_INT) +B_DEF (s390_vlgvg, vec_extractv2di, 0, 0, BT_FN_ULONGLONG_UV2DI_INT) +B_DEF (s390_vlgvg_dbl, vec_extractv2df, 0, B_INT, BT_FN_DBL_V2DF_INT) + +OB_DEF (s390_vec_insert_and_zero, s390_vec_insert_and_zero_s8,s390_vec_insert_and_zero_dbl,BT_FN_OV4SI_INTCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_s8,s390_vllezb, 0, BT_OV_V16QI_SCHARCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_u8,s390_vllezb, 0, BT_OV_UV16QI_UCHARCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_s16,s390_vllezh, 0, BT_OV_V8HI_SHORTCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_u16,s390_vllezh, 0, BT_OV_UV8HI_USHORTCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_s32,s390_vllezf, 0, BT_OV_V4SI_INTCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_u32,s390_vllezf, 0, BT_OV_UV4SI_UINTCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_s64,s390_vllezg, 0, BT_OV_V2DI_LONGLONGCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_u64,s390_vllezg, 0, BT_OV_UV2DI_ULONGLONGCONSTPTR) +OB_DEF_VAR (s390_vec_insert_and_zero_dbl,s390_vllezg, 0, BT_OV_V2DF_DBLCONSTPTR) + +B_DEF (s390_vllezb, vec_insert_and_zerov16qi,0, 0, BT_FN_UV16QI_UCHARCONSTPTR) +B_DEF (s390_vllezh, vec_insert_and_zerov8hi,0, 0, BT_FN_UV8HI_USHORTCONSTPTR) +B_DEF (s390_vllezf, vec_insert_and_zerov4si,0, 0, BT_FN_UV4SI_UINTCONSTPTR) +B_DEF (s390_vllezg, vec_insert_and_zerov2di,0, 0, BT_FN_UV2DI_ULONGLONGCONSTPTR) + +OB_DEF (s390_vec_load_bndry, s390_vec_load_bndry_s8,s390_vec_load_bndry_dbl,BT_FN_OV4SI_INTCONSTPTR_INT) +OB_DEF_VAR (s390_vec_load_bndry_s8, s390_vlbb, O2_U3, BT_OV_V16QI_SCHARCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_u8, s390_vlbb, O2_U3, BT_OV_UV16QI_UCHARCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_s16, s390_vlbb, O2_U3, BT_OV_V8HI_SHORTCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_u16, s390_vlbb, O2_U3, BT_OV_UV8HI_USHORTCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_s32, s390_vlbb, O2_U3, BT_OV_V4SI_INTCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_u32, s390_vlbb, O2_U3, BT_OV_UV4SI_UINTCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_s64, s390_vlbb, O2_U3, BT_OV_V2DI_LONGLONGCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_u64, s390_vlbb, O2_U3, BT_OV_UV2DI_ULONGLONGCONSTPTR_USHORT) +OB_DEF_VAR (s390_vec_load_bndry_dbl, s390_vlbb, O2_U3, BT_OV_V2DF_DBLCONSTPTR_USHORT) + +B_DEF (s390_vlbb, vlbb, 0, O2_U3, BT_FN_UV16QI_UCHARCONSTPTR_USHORT) + +OB_DEF (s390_vec_load_pair, s390_vec_load_pair_s64,s390_vec_load_pair_u64,BT_FN_OV2DI_LONGLONG_LONGLONG) +OB_DEF_VAR (s390_vec_load_pair_s64, MAX, 0, BT_OV_V2DI_LONGLONG_LONGLONG) /* vlvgp */ +OB_DEF_VAR (s390_vec_load_pair_u64, MAX, 0, BT_OV_UV2DI_ULONGLONG_ULONGLONG) /* vlvgp */ + +OB_DEF (s390_vec_load_len, s390_vec_load_len_s8,s390_vec_load_len_dbl,BT_FN_OV4SI_INTCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_s8, s390_vll, 0, BT_OV_V16QI_SCHARCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_u8, s390_vll, 0, BT_OV_UV16QI_UCHARCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_s16, s390_vll, 0, BT_OV_V8HI_SHORTCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_u16, s390_vll, 0, BT_OV_UV8HI_USHORTCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_s32, s390_vll, 0, BT_OV_V4SI_INTCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_u32, s390_vll, 0, BT_OV_UV4SI_UINTCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_s64, s390_vll, 0, BT_OV_V2DI_LONGLONGCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_u64, s390_vll, 0, BT_OV_UV2DI_ULONGLONGCONSTPTR_UINT) +OB_DEF_VAR (s390_vec_load_len_dbl, s390_vll, 0, BT_OV_V2DF_DBLCONSTPTR_UINT) + +B_DEF (s390_vll, vllv16qi, 0, 0, BT_FN_V16QI_UINT_VOIDCONSTPTR) + +OB_DEF (s390_vec_mergeh, s390_vec_mergeh_s8, s390_vec_mergeh_dbl,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mergeh_s8, s390_vmrhb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mergeh_u8, s390_vmrhb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mergeh_b8, s390_vmrhb, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_mergeh_s16, s390_vmrhh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mergeh_u16, s390_vmrhh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mergeh_b16, s390_vmrhh, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_mergeh_s32, s390_vmrhf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_mergeh_u32, s390_vmrhf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mergeh_b32, s390_vmrhf, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_mergeh_s64, s390_vmrhg, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_mergeh_u64, s390_vmrhg, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_mergeh_b64, s390_vmrhg, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_mergeh_dbl, s390_vmrhg, 0, BT_OV_V2DF_V2DF_V2DF) + +B_DEF (s390_vmrhb, vec_mergehv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmrhh, vec_mergehv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmrhf, vec_mergehv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmrhg, vec_mergehv2di, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) + +OB_DEF (s390_vec_mergel, s390_vec_mergel_s8, s390_vec_mergel_dbl,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mergel_s8, s390_vmrlb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mergel_u8, s390_vmrlb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mergel_b8, s390_vmrlb, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_mergel_s16, s390_vmrlh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mergel_u16, s390_vmrlh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mergel_b16, s390_vmrlh, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_mergel_s32, s390_vmrlf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_mergel_u32, s390_vmrlf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mergel_b32, s390_vmrlf, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_mergel_s64, s390_vmrlg, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_mergel_u64, s390_vmrlg, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_mergel_b64, s390_vmrlg, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_mergel_dbl, s390_vmrlg, 0, BT_OV_V2DF_V2DF_V2DF) + +B_DEF (s390_vmrlb, vec_mergelv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmrlh, vec_mergelv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmrlf, vec_mergelv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmrlg, vec_mergelv2di, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) + +OB_DEF (s390_vec_pack, s390_vec_pack_s16, s390_vec_pack_b64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_pack_s16, s390_vpkh, 0, BT_OV_V16QI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_pack_u16, s390_vpkh, 0, BT_OV_UV16QI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_pack_b16, s390_vpkh, 0, BT_OV_BV16QI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_pack_s32, s390_vpkf, 0, BT_OV_V8HI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_pack_u32, s390_vpkf, 0, BT_OV_UV8HI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_pack_b32, s390_vpkf, 0, BT_OV_BV8HI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_pack_s64, s390_vpkg, 0, BT_OV_V4SI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_pack_u64, s390_vpkg, 0, BT_OV_UV4SI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_pack_b64, s390_vpkg, 0, BT_OV_BV4SI_BV2DI_BV2DI) + +B_DEF (s390_vpkh, vec_packv8hi, 0, 0, BT_FN_UV16QI_UV8HI_UV8HI) +B_DEF (s390_vpkf, vec_packv4si, 0, 0, BT_FN_UV8HI_UV4SI_UV4SI) +B_DEF (s390_vpkg, vec_packv2di, 0, 0, BT_FN_UV4SI_UV2DI_UV2DI) + +OB_DEF (s390_vec_packs, s390_vec_packs_s16, s390_vec_packs_u64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_packs_s16, s390_vpksh, 0, BT_OV_V16QI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_packs_u16, s390_vpklsh, 0, BT_OV_UV16QI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_packs_s32, s390_vpksf, 0, BT_OV_V8HI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_packs_u32, s390_vpklsf, 0, BT_OV_UV8HI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_packs_s64, s390_vpksg, 0, BT_OV_V4SI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_packs_u64, s390_vpklsg, 0, BT_OV_UV4SI_UV2DI_UV2DI) + +B_DEF (s390_vpksh, vec_packsv8hi, 0, 0, BT_FN_V16QI_V8HI_V8HI) +B_DEF (s390_vpklsh, vec_packsuv8hi, 0, 0, BT_FN_UV16QI_UV8HI_UV8HI) +B_DEF (s390_vpksf, vec_packsv4si, 0, 0, BT_FN_V8HI_V4SI_V4SI) +B_DEF (s390_vpklsf, vec_packsuv4si, 0, 0, BT_FN_UV8HI_UV4SI_UV4SI) +B_DEF (s390_vpksg, vec_packsv2di, 0, 0, BT_FN_V4SI_V2DI_V2DI) +B_DEF (s390_vpklsg, vec_packsuv2di, 0, 0, BT_FN_UV4SI_UV2DI_UV2DI) + +OB_DEF (s390_vec_packs_cc, s390_vec_packs_cc_s16,s390_vec_packs_cc_u64,BT_FN_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_s16, s390_vpkshs, 0, BT_OV_V16QI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_u16, s390_vpklshs, 0, BT_OV_UV16QI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_s32, s390_vpksfs, 0, BT_OV_V8HI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_u32, s390_vpklsfs, 0, BT_OV_UV8HI_UV4SI_UV4SI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_s64, s390_vpksgs, 0, BT_OV_V4SI_V2DI_V2DI_INTPTR) +OB_DEF_VAR (s390_vec_packs_cc_u64, s390_vpklsgs, 0, BT_OV_UV4SI_UV2DI_UV2DI_INTPTR) + +B_DEF (s390_vpkshs, vec_packs_ccv8hi, 0, 0, BT_FN_V16QI_V8HI_V8HI_INTPTR) +B_DEF (s390_vpklshs, vec_packsu_ccv8hi, 0, 0, BT_FN_UV16QI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vpksfs, vec_packs_ccv4si, 0, 0, BT_FN_V8HI_V4SI_V4SI_INTPTR) +B_DEF (s390_vpklsfs, vec_packsu_ccv4si, 0, 0, BT_FN_UV8HI_UV4SI_UV4SI_INTPTR) +B_DEF (s390_vpksgs, vec_packs_ccv2di, 0, 0, BT_FN_V4SI_V2DI_V2DI_INTPTR) +B_DEF (s390_vpklsgs, vec_packsu_ccv2di, 0, 0, BT_FN_UV4SI_UV2DI_UV2DI_INTPTR) + +OB_DEF (s390_vec_packsu, s390_vec_packsu_s16,s390_vec_packsu_u64,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_packsu_s16, s390_vec_packsu_u16,0, BT_OV_UV16QI_V8HI_V8HI) /* vpklsh */ +OB_DEF_VAR (s390_vec_packsu_u16, s390_vpklsh, 0, BT_OV_UV16QI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_packsu_s32, s390_vec_packsu_u32,0, BT_OV_UV8HI_V4SI_V4SI) /* vpklsf */ +OB_DEF_VAR (s390_vec_packsu_u32, s390_vpklsf, 0, BT_OV_UV8HI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_packsu_s64, s390_vec_packsu_u64,0, BT_OV_UV4SI_V2DI_V2DI) /* vpklsg */ +OB_DEF_VAR (s390_vec_packsu_u64, s390_vpklsg, 0, BT_OV_UV4SI_UV2DI_UV2DI) + +B_DEF (s390_vec_packsu_u16, vec_packsu_uv8hi, 0, B_INT, BT_FN_UV16QI_UV8HI_UV8HI) /* vpklsh */ +B_DEF (s390_vec_packsu_u32, vec_packsu_uv4si, 0, B_INT, BT_FN_UV8HI_UV4SI_UV4SI) /* vpklsf */ +B_DEF (s390_vec_packsu_u64, vec_packsu_uv2di, 0, B_INT, BT_FN_UV4SI_UV2DI_UV2DI) /* vpklsg */ + +OB_DEF (s390_vec_packsu_cc, s390_vec_packsu_cc_u16,s390_vec_packsu_cc_u64,BT_FN_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vec_packsu_cc_u16, s390_vpklshs, 0, BT_OV_UV16QI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vec_packsu_cc_u32, s390_vpklsfs, 0, BT_OV_UV8HI_UV4SI_UV4SI_INTPTR) +OB_DEF_VAR (s390_vec_packsu_cc_u64, s390_vpklsgs, 0, BT_OV_UV4SI_UV2DI_UV2DI_INTPTR) + +OB_DEF (s390_vec_perm, s390_vec_perm_s8, s390_vec_perm_dbl, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_perm_s8, s390_vperm, 0, BT_OV_V16QI_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_perm_b8, s390_vperm, 0, BT_OV_BV16QI_BV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_perm_u8, s390_vperm, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_perm_s16, s390_vperm, 0, BT_OV_V8HI_V8HI_V8HI_UV16QI) +OB_DEF_VAR (s390_vec_perm_b16, s390_vperm, 0, BT_OV_BV8HI_BV8HI_BV8HI_UV16QI) +OB_DEF_VAR (s390_vec_perm_u16, s390_vperm, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_perm_s32, s390_vperm, 0, BT_OV_V4SI_V4SI_V4SI_UV16QI) +OB_DEF_VAR (s390_vec_perm_b32, s390_vperm, 0, BT_OV_BV4SI_BV4SI_BV4SI_UV16QI) +OB_DEF_VAR (s390_vec_perm_u32, s390_vperm, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV16QI) +OB_DEF_VAR (s390_vec_perm_s64, s390_vperm, 0, BT_OV_V2DI_V2DI_V2DI_UV16QI) +OB_DEF_VAR (s390_vec_perm_b64, s390_vperm, 0, BT_OV_BV2DI_BV2DI_BV2DI_UV16QI) +OB_DEF_VAR (s390_vec_perm_u64, s390_vperm, 0, BT_OV_UV2DI_UV2DI_UV2DI_UV16QI) +OB_DEF_VAR (s390_vec_perm_dbl, s390_vperm, 0, BT_OV_V2DF_V2DF_V2DF_UV16QI) + +B_DEF (s390_vperm, vec_permv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_permi, s390_vec_permi_s64, s390_vec_permi_dbl, BT_FN_OV4SI_OV4SI_OV4SI_INT) +OB_DEF_VAR (s390_vec_permi_s64, s390_vpdi, O3_U2, BT_OV_V2DI_V2DI_V2DI_INT) +OB_DEF_VAR (s390_vec_permi_b64, s390_vpdi, O3_U2, BT_OV_BV2DI_BV2DI_BV2DI_INT) +OB_DEF_VAR (s390_vec_permi_u64, s390_vpdi, O3_U2, BT_OV_UV2DI_UV2DI_UV2DI_INT) +OB_DEF_VAR (s390_vec_permi_dbl, s390_vpdi, O3_U2, BT_OV_V2DF_V2DF_V2DF_INT) + +B_DEF (s390_vpdi, vec_permiv2di, 0, O3_U2, BT_FN_UV2DI_UV2DI_UV2DI_INT) + +OB_DEF (s390_vec_splat, s390_vec_splat2_s8, s390_vec_splat2_dbl,BT_FN_OV4SI_OV4SI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_s8, s390_vrepb, O2_U4, BT_OV_V16QI_V16QI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_b8, s390_vrepb, O2_U4, BT_OV_BV16QI_BV16QI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_u8, s390_vrepb, O2_U4, BT_OV_UV16QI_UV16QI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_s16, s390_vreph, O2_U3, BT_OV_V8HI_V8HI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_b16, s390_vreph, O2_U3, BT_OV_BV8HI_BV8HI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_u16, s390_vreph, O2_U3, BT_OV_UV8HI_UV8HI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_s32, s390_vrepf, O2_U2, BT_OV_V4SI_V4SI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_b32, s390_vrepf, O2_U2, BT_OV_BV4SI_BV4SI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_u32, s390_vrepf, O2_U2, BT_OV_UV4SI_UV4SI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_s64, s390_vrepg, O2_U1, BT_OV_V2DI_V2DI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_b64, s390_vrepg, O2_U1, BT_OV_BV2DI_BV2DI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_u64, s390_vrepg, O2_U1, BT_OV_UV2DI_UV2DI_UCHAR) +OB_DEF_VAR (s390_vec_splat2_dbl, s390_vrepg, O2_U1, BT_OV_V2DF_V2DF_UCHAR) + +B_DEF (s390_vrepb, vec_splatv16qi, 0, O2_U4, BT_FN_UV16QI_UV16QI_UCHAR) +B_DEF (s390_vreph, vec_splatv8hi, 0, O2_U3, BT_FN_UV8HI_UV8HI_UCHAR) +B_DEF (s390_vrepf, vec_splatv4si, 0, O2_U2, BT_FN_UV4SI_UV4SI_UCHAR) +B_DEF (s390_vrepg, vec_splatv2di, 0, O2_U1, BT_FN_UV2DI_UV2DI_UCHAR) + +OB_DEF (s390_vec_scatter_element, s390_vec_scatter_element_s32,s390_vec_scatter_element_dbl,BT_FN_VOID_V4SI_V4SI_INTPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_s32,s390_vscef, O4_U2, BT_OV_VOID_V4SI_UV4SI_INTPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_b32,s390_vscef, O4_U2, BT_OV_VOID_BV4SI_UV4SI_UINTPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_u32,s390_vscef, O4_U2, BT_OV_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_s64,s390_vsceg, O4_U1, BT_OV_VOID_V2DI_UV2DI_LONGLONGPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_b64,s390_vsceg, O4_U1, BT_OV_VOID_BV2DI_UV2DI_ULONGLONGPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_u64,s390_vsceg, O4_U1, BT_OV_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG) +OB_DEF_VAR (s390_vec_scatter_element_dbl,s390_vsceg, O4_U1, BT_OV_VOID_V2DF_UV2DI_DBLPTR_ULONGLONG) + +B_DEF (s390_vscef, vec_scatter_elementv4si,0, O4_U2, BT_FN_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG) +B_DEF (s390_vsceg, vec_scatter_elementv2di,0, O4_U1, BT_FN_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG) + +OB_DEF (s390_vec_sel, s390_vec_sel_b8_a, s390_vec_sel_dbl_b, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sel_b8_a, s390_vsel, 0, BT_OV_BV16QI_BV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sel_b8_b, s390_vsel, 0, BT_OV_BV16QI_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_sel_s8_a, s390_vsel, 0, BT_OV_V16QI_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_sel_s8_b, s390_vsel, 0, BT_OV_V16QI_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_sel_u8_a, s390_vsel, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sel_u8_b, s390_vsel, 0, BT_OV_UV16QI_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_sel_b16_a, s390_vsel, 0, BT_OV_BV8HI_BV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sel_b16_b, s390_vsel, 0, BT_OV_BV8HI_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_sel_s16_a, s390_vsel, 0, BT_OV_V8HI_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_sel_s16_b, s390_vsel, 0, BT_OV_V8HI_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_sel_u16_a, s390_vsel, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sel_u16_b, s390_vsel, 0, BT_OV_UV8HI_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_sel_b32_a, s390_vsel, 0, BT_OV_BV4SI_BV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sel_b32_b, s390_vsel, 0, BT_OV_BV4SI_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_sel_s32_a, s390_vsel, 0, BT_OV_V4SI_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_sel_s32_b, s390_vsel, 0, BT_OV_V4SI_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_sel_u32_a, s390_vsel, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sel_u32_b, s390_vsel, 0, BT_OV_UV4SI_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_sel_b64_a, s390_vsel, 0, BT_OV_BV2DI_BV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_sel_b64_b, s390_vsel, 0, BT_OV_BV2DI_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_sel_s64_a, s390_vsel, 0, BT_OV_V2DI_V2DI_V2DI_UV2DI) +OB_DEF_VAR (s390_vec_sel_s64_b, s390_vsel, 0, BT_OV_V2DI_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_sel_u64_a, s390_vsel, 0, BT_OV_UV2DI_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_sel_u64_b, s390_vsel, 0, BT_OV_UV2DI_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_sel_dbl_a, s390_vsel, 0, BT_OV_V2DF_V2DF_V2DF_UV2DI) +OB_DEF_VAR (s390_vec_sel_dbl_b, s390_vsel, 0, BT_OV_V2DF_V2DF_V2DF_BV2DI) + +B_DEF (s390_vsel, vec_selv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_extend_s64, s390_vec_extend_s64_s8,s390_vec_extend_s64_s32,BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_extend_s64_s8, s390_vsegb, 0, BT_OV_V2DI_V16QI) +OB_DEF_VAR (s390_vec_extend_s64_s16, s390_vsegh, 0, BT_OV_V2DI_V8HI) +OB_DEF_VAR (s390_vec_extend_s64_s32, s390_vsegf, 0, BT_OV_V2DI_V4SI) + +B_DEF (s390_vsegb, vec_extendv16qi, 0, 0, BT_FN_V2DI_V16QI) +B_DEF (s390_vsegh, vec_extendv8hi, 0, 0, BT_FN_V2DI_V8HI) +B_DEF (s390_vsegf, vec_extendv4si, 0, 0, BT_FN_V2DI_V4SI) + +OB_DEF (s390_vec_xstd2, s390_vec_xstd2_s8, s390_vec_xstd2_dbl, BT_FN_VOID_OV4SI_INT_VOIDPTR) +OB_DEF_VAR (s390_vec_xstd2_s8, MAX, O2_LIT, BT_OV_VOID_V16QI_LONG_SCHARPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_u8, MAX, O2_LIT, BT_OV_VOID_UV16QI_LONG_UCHARPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_s16, MAX, O2_LIT, BT_OV_VOID_V8HI_LONG_SHORTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_u16, MAX, O2_LIT, BT_OV_VOID_UV8HI_LONG_USHORTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_s32, MAX, O2_LIT, BT_OV_VOID_V4SI_LONG_INTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_u32, MAX, O2_LIT, BT_OV_VOID_UV4SI_LONG_UINTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_s64, MAX, O2_LIT, BT_OV_VOID_V2DI_LONG_LONGLONGPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_u64, MAX, O2_LIT, BT_OV_VOID_UV2DI_LONG_ULONGLONGPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstd2_dbl, MAX, O2_LIT, BT_OV_VOID_V2DF_LONG_DBLPTR) /* vst */ + +OB_DEF (s390_vec_xstw4, s390_vec_xstw4_s8, s390_vec_xstw4_u32, BT_FN_VOID_OV4SI_INT_VOIDPTR) +OB_DEF_VAR (s390_vec_xstw4_s8, MAX, O2_LIT, BT_OV_VOID_V16QI_LONG_SCHARPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstw4_u8, MAX, O2_LIT, BT_OV_VOID_UV16QI_LONG_UCHARPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstw4_s16, MAX, O2_LIT, BT_OV_VOID_V8HI_LONG_SHORTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstw4_u16, MAX, O2_LIT, BT_OV_VOID_UV8HI_LONG_USHORTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstw4_s32, MAX, O2_LIT, BT_OV_VOID_V4SI_LONG_INTPTR) /* vst */ +OB_DEF_VAR (s390_vec_xstw4_u32, MAX, O2_LIT, BT_OV_VOID_UV4SI_LONG_UINTPTR) /* vst */ + +OB_DEF (s390_vec_store_len, s390_vec_store_len_s8,s390_vec_store_len_dbl,BT_FN_VOID_OV4SI_VOIDPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_s8, s390_vstl, 0, BT_OV_VOID_V16QI_SCHARPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_u8, s390_vstl, 0, BT_OV_VOID_UV16QI_UCHARPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_s16, s390_vstl, 0, BT_OV_VOID_V8HI_SHORTPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_u16, s390_vstl, 0, BT_OV_VOID_UV8HI_USHORTPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_s32, s390_vstl, 0, BT_OV_VOID_V4SI_INTPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_u32, s390_vstl, 0, BT_OV_VOID_UV4SI_UINTPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_s64, s390_vstl, 0, BT_OV_VOID_V2DI_LONGLONGPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_u64, s390_vstl, 0, BT_OV_VOID_UV2DI_ULONGLONGPTR_UINT) +OB_DEF_VAR (s390_vec_store_len_dbl, s390_vstl, 0, BT_OV_VOID_V2DF_DBLPTR_UINT) + +B_DEF (s390_vstl, vstlv16qi, 0, 0, BT_FN_VOID_V16QI_UINT_VOIDPTR) + +OB_DEF (s390_vec_unpackh, s390_vec_unpackh_s8,s390_vec_unpackh_u32,BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_unpackh_s8, s390_vuphb, 0, BT_OV_V8HI_V16QI) +OB_DEF_VAR (s390_vec_unpackh_b8, s390_vuphb, 0, BT_OV_BV8HI_BV16QI) +OB_DEF_VAR (s390_vec_unpackh_u8, s390_vuplhb, 0, BT_OV_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_unpackh_s16, s390_vuphh, 0, BT_OV_V4SI_V8HI) +OB_DEF_VAR (s390_vec_unpackh_b16, s390_vuphh, 0, BT_OV_BV4SI_BV8HI) +OB_DEF_VAR (s390_vec_unpackh_u16, s390_vuplhh, 0, BT_OV_UV4SI_UV8HI) +OB_DEF_VAR (s390_vec_unpackh_s32, s390_vuphf, 0, BT_OV_V2DI_V4SI) +OB_DEF_VAR (s390_vec_unpackh_b32, s390_vuphf, 0, BT_OV_BV2DI_BV4SI) +OB_DEF_VAR (s390_vec_unpackh_u32, s390_vuplhf, 0, BT_OV_UV2DI_UV4SI) + +B_DEF (s390_vuphb, vec_unpackhv16qi, 0, 0, BT_FN_V8HI_V16QI) +B_DEF (s390_vuplhb, vec_unpackh_lv16qi, 0, 0, BT_FN_UV8HI_UV16QI) +B_DEF (s390_vuphh, vec_unpackhv8hi, 0, 0, BT_FN_V4SI_V8HI) +B_DEF (s390_vuplhh, vec_unpackh_lv8hi, 0, 0, BT_FN_UV4SI_UV8HI) +B_DEF (s390_vuphf, vec_unpackhv4si, 0, 0, BT_FN_V2DI_V4SI) +B_DEF (s390_vuplhf, vec_unpackh_lv4si, 0, 0, BT_FN_UV2DI_UV4SI) + +OB_DEF (s390_vec_unpackl, s390_vec_unpackl_s8,s390_vec_unpackl_u32,BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_unpackl_s8, s390_vuplb, 0, BT_OV_V8HI_V16QI) +OB_DEF_VAR (s390_vec_unpackl_b8, s390_vuplb, 0, BT_OV_BV8HI_BV16QI) +OB_DEF_VAR (s390_vec_unpackl_u8, s390_vupllb, 0, BT_OV_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_unpackl_s16, s390_vuplhw, 0, BT_OV_V4SI_V8HI) +OB_DEF_VAR (s390_vec_unpackl_b16, s390_vupllh, 0, BT_OV_BV4SI_BV8HI) +OB_DEF_VAR (s390_vec_unpackl_u16, s390_vupllh, 0, BT_OV_UV4SI_UV8HI) +OB_DEF_VAR (s390_vec_unpackl_s32, s390_vuplf, 0, BT_OV_V2DI_V4SI) +OB_DEF_VAR (s390_vec_unpackl_b32, s390_vuplf, 0, BT_OV_BV2DI_BV4SI) +OB_DEF_VAR (s390_vec_unpackl_u32, s390_vupllf, 0, BT_OV_UV2DI_UV4SI) + +B_DEF (s390_vuplb, vec_unpacklv16qi, 0, 0, BT_FN_V8HI_V16QI) +B_DEF (s390_vupllb, vec_unpackl_lv16qi, 0, 0, BT_FN_UV8HI_UV16QI) +B_DEF (s390_vuplhw, vec_unpacklv8hi, 0, 0, BT_FN_V4SI_V8HI) +B_DEF (s390_vupllh, vec_unpackl_lv8hi, 0, 0, BT_FN_UV4SI_UV8HI) +B_DEF (s390_vuplf, vec_unpacklv4si, 0, 0, BT_FN_V2DI_V4SI) +B_DEF (s390_vupllf, vec_unpackl_lv4si, 0, 0, BT_FN_UV2DI_UV4SI) +B_DEF (s390_vaq, vec_add_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_addc, s390_vec_addc_u8, s390_vec_addc_u64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_addc_u8, s390_vaccb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_addc_u16, s390_vacch, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_addc_u32, s390_vaccf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_addc_u64, s390_vaccg, 0, BT_OV_UV2DI_UV2DI_UV2DI) + +B_DEF (s390_vaccb, vec_addcv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vacch, vec_addcv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vaccf, vec_addcv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vaccg, vec_addcv2di, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) +B_DEF (s390_vaccq, vec_addc_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vacq, vec_adde_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vacccq, vec_addec_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_and, s390_vec_and_b8, s390_vec_and_dbl_c, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_and_b8, s390_vn, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_and_s8_a, s390_vn, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_and_s8_b, s390_vn, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_and_s8_c, s390_vn, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_and_u8_a, s390_vn, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_and_u8_b, s390_vn, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_and_u8_c, s390_vn, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_and_b16, s390_vn, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_and_s16_a, s390_vn, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_and_s16_b, s390_vn, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_and_s16_c, s390_vn, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_and_u16_a, s390_vn, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_and_u16_b, s390_vn, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_and_u16_c, s390_vn, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_and_b32, s390_vn, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_and_s32_a, s390_vn, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_and_s32_b, s390_vn, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_and_s32_c, s390_vn, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_and_u32_a, s390_vn, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_and_u32_b, s390_vn, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_and_u32_c, s390_vn, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_and_b64, s390_vn, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_and_s64_a, s390_vn, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_and_s64_b, s390_vn, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_and_s64_c, s390_vn, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_and_u64_a, s390_vn, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_and_u64_b, s390_vn, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_and_u64_c, s390_vn, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_and_dbl_a, s390_vn, 0, BT_OV_V2DF_BV2DI_V2DF) +OB_DEF_VAR (s390_vec_and_dbl_b, s390_vn, 0, BT_OV_V2DF_V2DF_V2DF) +OB_DEF_VAR (s390_vec_and_dbl_c, s390_vn, 0, BT_OV_V2DF_V2DF_BV2DI) + +B_DEF (s390_vn, andv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_andc, s390_vec_andc_b8, s390_vec_andc_dbl_c,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_andc_b8, s390_vnc, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_andc_s8_a, s390_vnc, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_andc_s8_b, s390_vnc, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_andc_s8_c, s390_vnc, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_andc_u8_a, s390_vnc, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_andc_u8_b, s390_vnc, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_andc_u8_c, s390_vnc, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_andc_b16, s390_vnc, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_andc_s16_a, s390_vnc, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_andc_s16_b, s390_vnc, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_andc_s16_c, s390_vnc, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_andc_u16_a, s390_vnc, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_andc_u16_b, s390_vnc, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_andc_u16_c, s390_vnc, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_andc_b32, s390_vnc, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_andc_s32_a, s390_vnc, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_andc_s32_b, s390_vnc, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_andc_s32_c, s390_vnc, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_andc_u32_a, s390_vnc, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_andc_u32_b, s390_vnc, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_andc_u32_c, s390_vnc, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_andc_b64, s390_vnc, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_andc_s64_a, s390_vnc, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_andc_s64_b, s390_vnc, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_andc_s64_c, s390_vnc, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_andc_u64_a, s390_vnc, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_andc_u64_b, s390_vnc, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_andc_u64_c, s390_vnc, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_andc_dbl_a, s390_vnc, 0, BT_OV_V2DF_BV2DI_V2DF) +OB_DEF_VAR (s390_vec_andc_dbl_b, s390_vnc, 0, BT_OV_V2DF_V2DF_V2DF) +OB_DEF_VAR (s390_vec_andc_dbl_c, s390_vnc, 0, BT_OV_V2DF_V2DF_BV2DI) + +B_DEF (s390_vnc, vec_andcv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_avg, s390_vec_avg_s8, s390_vec_avg_u64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_avg_s8, s390_vavgb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_avg_u8, s390_vavglb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_avg_s16, s390_vavgh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_avg_u16, s390_vavglh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_avg_s32, s390_vavgf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_avg_u32, s390_vavglf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_avg_s64, s390_vavgg, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_avg_u64, s390_vavglg, 0, BT_OV_UV2DI_UV2DI_UV2DI) + +B_DEF (s390_vavgb, vec_avgv16qi, 0, 0, BT_FN_V16QI_V16QI_V16QI) +B_DEF (s390_vavglb, vec_avguv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vavgh, vec_avgv8hi, 0, 0, BT_FN_V8HI_V8HI_V8HI) +B_DEF (s390_vavglh, vec_avguv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vavgf, vec_avgv4si, 0, 0, BT_FN_V4SI_V4SI_V4SI) +B_DEF (s390_vavglf, vec_avguv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vavgg, vec_avgv2di, 0, 0, BT_FN_V2DI_V2DI_V2DI) +B_DEF (s390_vavglg, vec_avguv2di, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) + +B_DEF (s390_vcksm, vec_checksum, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) + +B_DEF (s390_vceqbs, vec_cmpeqv16qi_cc, 0, 0, BT_FN_V16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vceqhs, vec_cmpeqv8hi_cc, 0, 0, BT_FN_V8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vceqfs, vec_cmpeqv4si_cc, 0, 0, BT_FN_V4SI_UV4SI_UV4SI_INTPTR) +B_DEF (s390_vceqgs, vec_cmpeqv2di_cc, 0, 0, BT_FN_V2DI_UV2DI_UV2DI_INTPTR) +B_DEF (s390_vfcedbs, vec_cmpeqv2df_cc, 0, 0, BT_FN_V2DI_V2DF_V2DF_INTPTR) + +B_DEF (s390_vchbs, vec_cmphv16qi_cc, 0, 0, BT_FN_V16QI_V16QI_V16QI_INTPTR) +B_DEF (s390_vchlbs, vec_cmphlv16qi_cc, 0, 0, BT_FN_V16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vchhs, vec_cmphv8hi_cc, 0, 0, BT_FN_V8HI_V8HI_V8HI_INTPTR) +B_DEF (s390_vchlhs, vec_cmphlv8hi_cc, 0, 0, BT_FN_V8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vchfs, vec_cmphv4si_cc, 0, 0, BT_FN_V4SI_V4SI_V4SI_INTPTR) +B_DEF (s390_vchlfs, vec_cmphlv4si_cc, 0, 0, BT_FN_V4SI_UV4SI_UV4SI_INTPTR) +B_DEF (s390_vchgs, vec_cmphv2di_cc, 0, 0, BT_FN_V2DI_V2DI_V2DI_INTPTR) +B_DEF (s390_vchlgs, vec_cmphlv2di_cc, 0, 0, BT_FN_V2DI_UV2DI_UV2DI_INTPTR) +B_DEF (s390_vfchdbs, vec_cmphv2df_cc, 0, 0, BT_FN_V2DI_V2DF_V2DF_INTPTR) +B_DEF (s390_vfchedbs, vec_cmphev2df_cc, 0, 0, BT_FN_V2DI_V2DF_V2DF_INTPTR) + +B_DEF (vec_all_eqv16qi, vec_all_eqv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_eqv8hi, vec_all_eqv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_eqv4si, vec_all_eqv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_eqv2di, vec_all_eqv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_eqv2df, vec_all_eqv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_all_nev16qi, vec_all_nev16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_nev8hi, vec_all_nev8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_nev4si, vec_all_nev4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_nev2di, vec_all_nev2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_nev2df, vec_all_nev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_all_gev16qi, vec_all_gev16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_all_geuv16qi, vec_all_geuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_gev8hi, vec_all_gev8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_all_geuv8hi, vec_all_geuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_gev4si, vec_all_gev4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_all_geuv4si, vec_all_geuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_gev2di, vec_all_gev2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_all_geuv2di, vec_all_geuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_gev2df, vec_all_gev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_all_gtv16qi, vec_all_gtv16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_all_gtuv16qi, vec_all_gtuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_gtv8hi, vec_all_gtv8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_all_gtuv8hi, vec_all_gtuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_gtv4si, vec_all_gtv4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_all_gtuv4si, vec_all_gtuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_gtv2di, vec_all_gtv2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_all_gtuv2di, vec_all_gtuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_gtv2df, vec_all_gtv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_all_lev16qi, vec_all_lev16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_all_leuv16qi, vec_all_leuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_lev8hi, vec_all_lev8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_all_leuv8hi, vec_all_leuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_lev4si, vec_all_lev4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_all_leuv4si, vec_all_leuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_lev2di, vec_all_lev2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_all_leuv2di, vec_all_leuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_lev2df, vec_all_lev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_all_ltv16qi, vec_all_ltv16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_all_ltuv16qi, vec_all_ltuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_all_ltv8hi, vec_all_ltv8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_all_ltuv8hi, vec_all_ltuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_all_ltv4si, vec_all_ltv4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_all_ltuv4si, vec_all_ltuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_all_ltv2di, vec_all_ltv2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_all_ltuv2di, vec_all_ltuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_all_ltv2df, vec_all_ltv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_eq, s390_vec_all_eq_s8_a,s390_vec_all_eq_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_eq_s8_a, vec_all_eqv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_eq_s8_b, vec_all_eqv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_eq_b8_a, vec_all_eqv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_eq_b8_b, vec_all_eqv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_eq_b8_c, vec_all_eqv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_eq_u8_a, vec_all_eqv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_eq_u8_b, vec_all_eqv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_eq_s16_a, vec_all_eqv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_eq_s16_b, vec_all_eqv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_eq_b16_a, vec_all_eqv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_eq_b16_b, vec_all_eqv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_eq_b16_c, vec_all_eqv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_eq_u16_a, vec_all_eqv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_eq_u16_b, vec_all_eqv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_eq_s32_a, vec_all_eqv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_eq_s32_b, vec_all_eqv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_eq_b32_a, vec_all_eqv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_eq_b32_b, vec_all_eqv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_eq_b32_c, vec_all_eqv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_eq_u32_a, vec_all_eqv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_eq_u32_b, vec_all_eqv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_eq_s64_a, vec_all_eqv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_eq_s64_b, vec_all_eqv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_eq_b64_a, vec_all_eqv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_eq_b64_b, vec_all_eqv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_eq_b64_c, vec_all_eqv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_eq_u64_a, vec_all_eqv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_eq_u64_b, vec_all_eqv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_eq_dbl, vec_all_eqv2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_ne, s390_vec_all_ne_s8_a,s390_vec_all_ne_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_ne_s8_a, vec_all_nev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_ne_s8_b, vec_all_nev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ne_b8_a, vec_all_nev16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ne_b8_b, vec_all_nev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_ne_b8_c, vec_all_nev16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_ne_u8_a, vec_all_nev16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_ne_u8_b, vec_all_nev16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ne_s16_a, vec_all_nev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_ne_s16_b, vec_all_nev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ne_b16_a, vec_all_nev8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ne_b16_b, vec_all_nev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_ne_b16_c, vec_all_nev8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_ne_u16_a, vec_all_nev8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_ne_u16_b, vec_all_nev8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ne_s32_a, vec_all_nev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_ne_s32_b, vec_all_nev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ne_b32_a, vec_all_nev4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ne_b32_b, vec_all_nev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_ne_b32_c, vec_all_nev4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_ne_u32_a, vec_all_nev4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_ne_u32_b, vec_all_nev4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ne_s64_a, vec_all_nev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_ne_s64_b, vec_all_nev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ne_b64_a, vec_all_nev2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ne_b64_b, vec_all_nev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_ne_b64_c, vec_all_nev2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_ne_u64_a, vec_all_nev2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_ne_u64_b, vec_all_nev2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ne_dbl, vec_all_nev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_ge, s390_vec_all_ge_s8_a,s390_vec_all_ge_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_ge_s8_a, vec_all_gev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_ge_s8_b, vec_all_gev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ge_b8_a, vec_all_geuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ge_b8_b, vec_all_gev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_ge_b8_c, vec_all_geuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_ge_u8_a, vec_all_geuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_ge_u8_b, vec_all_geuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_ge_s16_a, vec_all_gev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_ge_s16_b, vec_all_gev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ge_b16_a, vec_all_geuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ge_b16_b, vec_all_gev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_ge_b16_c, vec_all_geuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_ge_u16_a, vec_all_geuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_ge_u16_b, vec_all_geuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_ge_s32_a, vec_all_gev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_ge_s32_b, vec_all_gev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ge_b32_a, vec_all_geuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ge_b32_b, vec_all_gev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_ge_b32_c, vec_all_geuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_ge_u32_a, vec_all_geuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_ge_u32_b, vec_all_geuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_ge_s64_a, vec_all_gev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_ge_s64_b, vec_all_gev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ge_b64_a, vec_all_geuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ge_b64_b, vec_all_gev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_ge_b64_c, vec_all_geuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_ge_u64_a, vec_all_geuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_ge_u64_b, vec_all_geuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_ge_dbl, vec_all_gev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_gt, s390_vec_all_gt_s8_a,s390_vec_all_gt_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_gt_s8_a, vec_all_gtv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_gt_s8_b, vec_all_gtv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_gt_b8_a, vec_all_gtuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_gt_b8_b, vec_all_gtv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_gt_b8_c, vec_all_gtuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_gt_u8_a, vec_all_gtuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_gt_u8_b, vec_all_gtuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_gt_s16_a, vec_all_gtv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_gt_s16_b, vec_all_gtv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_gt_b16_a, vec_all_gtuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_gt_b16_b, vec_all_gtv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_gt_b16_c, vec_all_gtuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_gt_u16_a, vec_all_gtuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_gt_u16_b, vec_all_gtuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_gt_s32_a, vec_all_gtv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_gt_s32_b, vec_all_gtv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_gt_b32_a, vec_all_gtuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_gt_b32_b, vec_all_gtv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_gt_b32_c, vec_all_gtuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_gt_u32_a, vec_all_gtuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_gt_u32_b, vec_all_gtuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_gt_s64_a, vec_all_gtv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_gt_s64_b, vec_all_gtv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_gt_b64_a, vec_all_gtuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_gt_b64_b, vec_all_gtv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_gt_b64_c, vec_all_gtuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_gt_u64_a, vec_all_gtuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_gt_u64_b, vec_all_gtuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_gt_dbl, vec_all_gtv2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_le, s390_vec_all_le_s8_a,s390_vec_all_le_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_le_s8_a, vec_all_lev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_le_s8_b, vec_all_lev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_le_b8_a, vec_all_leuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_le_b8_b, vec_all_lev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_le_b8_c, vec_all_leuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_le_u8_a, vec_all_leuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_le_u8_b, vec_all_leuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_le_s16_a, vec_all_lev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_le_s16_b, vec_all_lev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_le_b16_a, vec_all_leuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_le_b16_b, vec_all_lev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_le_b16_c, vec_all_leuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_le_u16_a, vec_all_leuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_le_u16_b, vec_all_leuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_le_s32_a, vec_all_lev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_le_s32_b, vec_all_lev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_le_b32_a, vec_all_leuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_le_b32_b, vec_all_lev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_le_b32_c, vec_all_leuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_le_u32_a, vec_all_leuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_le_u32_b, vec_all_leuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_le_s64_a, vec_all_lev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_le_s64_b, vec_all_lev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_le_b64_a, vec_all_leuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_le_b64_b, vec_all_lev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_le_b64_c, vec_all_leuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_le_u64_a, vec_all_leuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_le_u64_b, vec_all_leuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_le_dbl, vec_all_lev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_all_lt, s390_vec_all_lt_s8_a,s390_vec_all_lt_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_all_lt_s8_a, vec_all_ltv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_all_lt_s8_b, vec_all_ltv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_lt_b8_a, vec_all_ltuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_lt_b8_b, vec_all_ltv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_all_lt_b8_c, vec_all_ltuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_lt_u8_a, vec_all_ltuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_all_lt_u8_b, vec_all_ltuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_all_lt_s16_a, vec_all_ltv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_all_lt_s16_b, vec_all_ltv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_lt_b16_a, vec_all_ltuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_lt_b16_b, vec_all_ltv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_all_lt_b16_c, vec_all_ltuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_lt_u16_a, vec_all_ltuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_all_lt_u16_b, vec_all_ltuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_all_lt_s32_a, vec_all_ltv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_all_lt_s32_b, vec_all_ltv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_lt_b32_a, vec_all_ltuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_lt_b32_b, vec_all_ltv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_all_lt_b32_c, vec_all_ltuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_lt_u32_a, vec_all_ltuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_all_lt_u32_b, vec_all_ltuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_all_lt_s64_a, vec_all_ltv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_all_lt_s64_b, vec_all_ltv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_lt_b64_a, vec_all_ltuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_lt_b64_b, vec_all_ltv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_all_lt_b64_c, vec_all_ltuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_lt_u64_a, vec_all_ltuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_all_lt_u64_b, vec_all_ltuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_all_lt_dbl, vec_all_ltv2df, 0, BT_OV_INT_V2DF_V2DF) + +B_DEF (vec_any_eqv16qi, vec_any_eqv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_eqv8hi, vec_any_eqv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_eqv4si, vec_any_eqv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_eqv2di, vec_any_eqv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_eqv2df, vec_any_eqv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_any_nev16qi, vec_any_nev16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_nev8hi, vec_any_nev8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_nev4si, vec_any_nev4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_nev2di, vec_any_nev2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_nev2df, vec_any_nev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_any_gev16qi, vec_any_gev16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_any_geuv16qi, vec_any_geuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_gev8hi, vec_any_gev8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_any_geuv8hi, vec_any_geuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_gev4si, vec_any_gev4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_any_geuv4si, vec_any_geuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_gev2di, vec_any_gev2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_any_geuv2di, vec_any_geuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_gev2df, vec_any_gev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_any_gtv16qi, vec_any_gtv16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_any_gtuv16qi, vec_any_gtuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_gtv8hi, vec_any_gtv8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_any_gtuv8hi, vec_any_gtuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_gtv4si, vec_any_gtv4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_any_gtuv4si, vec_any_gtuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_gtv2di, vec_any_gtv2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_any_gtuv2di, vec_any_gtuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_gtv2df, vec_any_gtv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_any_lev16qi, vec_any_lev16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_any_leuv16qi, vec_any_leuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_lev8hi, vec_any_lev8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_any_leuv8hi, vec_any_leuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_lev4si, vec_any_lev4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_any_leuv4si, vec_any_leuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_lev2di, vec_any_lev2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_any_leuv2di, vec_any_leuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_lev2df, vec_any_lev2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +B_DEF (vec_any_ltv16qi, vec_any_ltv16qi, 0, B_INT, BT_FN_INT_V16QI_V16QI) +B_DEF (vec_any_ltuv16qi, vec_any_ltuv16qi, 0, B_INT, BT_FN_INT_UV16QI_UV16QI) +B_DEF (vec_any_ltv8hi, vec_any_ltv8hi, 0, B_INT, BT_FN_INT_V8HI_V8HI) +B_DEF (vec_any_ltuv8hi, vec_any_ltuv8hi, 0, B_INT, BT_FN_INT_UV8HI_UV8HI) +B_DEF (vec_any_ltv4si, vec_any_ltv4si, 0, B_INT, BT_FN_INT_V4SI_V4SI) +B_DEF (vec_any_ltuv4si, vec_any_ltuv4si, 0, B_INT, BT_FN_INT_UV4SI_UV4SI) +B_DEF (vec_any_ltv2di, vec_any_ltv2di, 0, B_INT, BT_FN_INT_V2DI_V2DI) +B_DEF (vec_any_ltuv2di, vec_any_ltuv2di, 0, B_INT, BT_FN_INT_UV2DI_UV2DI) +B_DEF (vec_any_ltv2df, vec_any_ltv2df, 0, B_INT, BT_FN_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_eq, s390_vec_any_eq_s8_a,s390_vec_any_eq_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_eq_s8_a, vec_any_eqv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_eq_s8_b, vec_any_eqv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_eq_b8_a, vec_any_eqv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_eq_b8_b, vec_any_eqv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_eq_b8_c, vec_any_eqv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_eq_u8_a, vec_any_eqv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_eq_u8_b, vec_any_eqv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_eq_s16_a, vec_any_eqv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_eq_s16_b, vec_any_eqv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_eq_b16_a, vec_any_eqv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_eq_b16_b, vec_any_eqv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_eq_b16_c, vec_any_eqv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_eq_u16_a, vec_any_eqv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_eq_u16_b, vec_any_eqv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_eq_s32_a, vec_any_eqv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_eq_s32_b, vec_any_eqv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_eq_b32_a, vec_any_eqv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_eq_b32_b, vec_any_eqv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_eq_b32_c, vec_any_eqv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_eq_u32_a, vec_any_eqv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_eq_u32_b, vec_any_eqv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_eq_s64_a, vec_any_eqv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_eq_s64_b, vec_any_eqv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_eq_b64_a, vec_any_eqv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_eq_b64_b, vec_any_eqv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_eq_b64_c, vec_any_eqv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_eq_u64_a, vec_any_eqv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_eq_u64_b, vec_any_eqv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_eq_dbl, vec_any_eqv2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_ne, s390_vec_any_ne_s8_a,s390_vec_any_ne_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_ne_s8_a, vec_any_nev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_ne_s8_b, vec_any_nev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ne_b8_a, vec_any_nev16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ne_b8_b, vec_any_nev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_ne_b8_c, vec_any_nev16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_ne_u8_a, vec_any_nev16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_ne_u8_b, vec_any_nev16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ne_s16_a, vec_any_nev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_ne_s16_b, vec_any_nev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ne_b16_a, vec_any_nev8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ne_b16_b, vec_any_nev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_ne_b16_c, vec_any_nev8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_ne_u16_a, vec_any_nev8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_ne_u16_b, vec_any_nev8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ne_s32_a, vec_any_nev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_ne_s32_b, vec_any_nev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ne_b32_a, vec_any_nev4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ne_b32_b, vec_any_nev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_ne_b32_c, vec_any_nev4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_ne_u32_a, vec_any_nev4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_ne_u32_b, vec_any_nev4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ne_s64_a, vec_any_nev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_ne_s64_b, vec_any_nev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ne_b64_a, vec_any_nev2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ne_b64_b, vec_any_nev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_ne_b64_c, vec_any_nev2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_ne_u64_a, vec_any_nev2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_ne_u64_b, vec_any_nev2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ne_dbl, vec_any_nev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_ge, s390_vec_any_ge_s8_a,s390_vec_any_ge_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_ge_s8_a, vec_any_gev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_ge_s8_b, vec_any_gev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ge_b8_a, vec_any_geuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ge_b8_b, vec_any_gev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_ge_b8_c, vec_any_geuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_ge_u8_a, vec_any_geuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_ge_u8_b, vec_any_geuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_ge_s16_a, vec_any_gev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_ge_s16_b, vec_any_gev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ge_b16_a, vec_any_geuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ge_b16_b, vec_any_gev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_ge_b16_c, vec_any_geuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_ge_u16_a, vec_any_geuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_ge_u16_b, vec_any_geuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_ge_s32_a, vec_any_gev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_ge_s32_b, vec_any_gev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ge_b32_a, vec_any_geuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ge_b32_b, vec_any_gev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_ge_b32_c, vec_any_geuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_ge_u32_a, vec_any_geuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_ge_u32_b, vec_any_geuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_ge_s64_a, vec_any_gev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_ge_s64_b, vec_any_gev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ge_b64_a, vec_any_geuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ge_b64_b, vec_any_gev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_ge_b64_c, vec_any_geuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_ge_u64_a, vec_any_geuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_ge_u64_b, vec_any_geuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_ge_dbl, vec_any_gev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_gt, s390_vec_any_gt_s8_a,s390_vec_any_gt_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_gt_s8_a, vec_any_gtv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_gt_s8_b, vec_any_gtv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_gt_b8_a, vec_any_gtuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_gt_b8_b, vec_any_gtv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_gt_b8_c, vec_any_gtuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_gt_u8_a, vec_any_gtuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_gt_u8_b, vec_any_gtuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_gt_s16_a, vec_any_gtv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_gt_s16_b, vec_any_gtv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_gt_b16_a, vec_any_gtuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_gt_b16_b, vec_any_gtv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_gt_b16_c, vec_any_gtuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_gt_u16_a, vec_any_gtuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_gt_u16_b, vec_any_gtuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_gt_s32_a, vec_any_gtv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_gt_s32_b, vec_any_gtv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_gt_b32_a, vec_any_gtuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_gt_b32_b, vec_any_gtv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_gt_b32_c, vec_any_gtuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_gt_u32_a, vec_any_gtuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_gt_u32_b, vec_any_gtuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_gt_s64_a, vec_any_gtv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_gt_s64_b, vec_any_gtv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_gt_b64_a, vec_any_gtuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_gt_b64_b, vec_any_gtv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_gt_b64_c, vec_any_gtuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_gt_u64_a, vec_any_gtuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_gt_u64_b, vec_any_gtuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_gt_dbl, vec_any_gtv2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_le, s390_vec_any_le_s8_a,s390_vec_any_le_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_le_s8_a, vec_any_lev16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_le_s8_b, vec_any_lev16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_le_b8_a, vec_any_leuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_le_b8_b, vec_any_lev16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_le_b8_c, vec_any_leuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_le_u8_a, vec_any_leuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_le_u8_b, vec_any_leuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_le_s16_a, vec_any_lev8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_le_s16_b, vec_any_lev8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_le_b16_a, vec_any_leuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_le_b16_b, vec_any_lev8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_le_b16_c, vec_any_leuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_le_u16_a, vec_any_leuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_le_u16_b, vec_any_leuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_le_s32_a, vec_any_lev4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_le_s32_b, vec_any_lev4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_le_b32_a, vec_any_leuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_le_b32_b, vec_any_lev4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_le_b32_c, vec_any_leuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_le_u32_a, vec_any_leuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_le_u32_b, vec_any_leuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_le_s64_a, vec_any_lev2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_le_s64_b, vec_any_lev2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_le_b64_a, vec_any_leuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_le_b64_b, vec_any_lev2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_le_b64_c, vec_any_leuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_le_u64_a, vec_any_leuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_le_u64_b, vec_any_leuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_le_dbl, vec_any_lev2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_any_lt, s390_vec_any_lt_s8_a,s390_vec_any_lt_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_any_lt_s8_a, vec_any_ltv16qi, 0, BT_OV_INT_V16QI_V16QI) +OB_DEF_VAR (s390_vec_any_lt_s8_b, vec_any_ltv16qi, 0, BT_OV_INT_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_lt_b8_a, vec_any_ltuv16qi, 0, BT_OV_INT_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_lt_b8_b, vec_any_ltv16qi, 0, BT_OV_INT_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_any_lt_b8_c, vec_any_ltuv16qi, 0, BT_OV_INT_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_lt_u8_a, vec_any_ltuv16qi, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_any_lt_u8_b, vec_any_ltuv16qi, 0, BT_OV_INT_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_any_lt_s16_a, vec_any_ltv8hi, 0, BT_OV_INT_V8HI_V8HI) +OB_DEF_VAR (s390_vec_any_lt_s16_b, vec_any_ltv8hi, 0, BT_OV_INT_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_lt_b16_a, vec_any_ltuv8hi, 0, BT_OV_INT_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_lt_b16_b, vec_any_ltv8hi, 0, BT_OV_INT_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_any_lt_b16_c, vec_any_ltuv8hi, 0, BT_OV_INT_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_lt_u16_a, vec_any_ltuv8hi, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_any_lt_u16_b, vec_any_ltuv8hi, 0, BT_OV_INT_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_any_lt_s32_a, vec_any_ltv4si, 0, BT_OV_INT_V4SI_V4SI) +OB_DEF_VAR (s390_vec_any_lt_s32_b, vec_any_ltv4si, 0, BT_OV_INT_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_lt_b32_a, vec_any_ltuv4si, 0, BT_OV_INT_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_lt_b32_b, vec_any_ltv4si, 0, BT_OV_INT_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_any_lt_b32_c, vec_any_ltuv4si, 0, BT_OV_INT_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_lt_u32_a, vec_any_ltuv4si, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_any_lt_u32_b, vec_any_ltuv4si, 0, BT_OV_INT_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_any_lt_s64_a, vec_any_ltv2di, 0, BT_OV_INT_V2DI_V2DI) +OB_DEF_VAR (s390_vec_any_lt_s64_b, vec_any_ltv2di, 0, BT_OV_INT_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_lt_b64_a, vec_any_ltuv2di, 0, BT_OV_INT_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_lt_b64_b, vec_any_ltv2di, 0, BT_OV_INT_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_any_lt_b64_c, vec_any_ltuv2di, 0, BT_OV_INT_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_lt_u64_a, vec_any_ltuv2di, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_any_lt_u64_b, vec_any_ltuv2di, 0, BT_OV_INT_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_any_lt_dbl, vec_any_ltv2df, 0, BT_OV_INT_V2DF_V2DF) + +OB_DEF (s390_vec_cmpeq, s390_vec_cmpeq_s8, s390_vec_cmpeq_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cmpeq_s8, s390_vceqb, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_cmpeq_u8, s390_vceqb, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cmpeq_b8, s390_vceqb, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_cmpeq_s16, s390_vceqh, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_cmpeq_u16, s390_vceqh, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cmpeq_b16, s390_vceqh, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_cmpeq_s32, s390_vceqf, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_cmpeq_u32, s390_vceqf, 0, BT_OV_BV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cmpeq_b32, s390_vceqf, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_cmpeq_s64, s390_vceqg, 0, BT_OV_BV2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_cmpeq_u64, s390_vceqg, 0, BT_OV_BV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_cmpeq_b64, s390_vceqg, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_cmpeq_dbl, s390_vfcedb, 0, BT_OV_BV2DI_V2DF_V2DF) + +B_DEF (s390_vceqb, vec_cmpeqv16qi, 0, 0, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (s390_vceqh, vec_cmpeqv8hi, 0, 0, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (s390_vceqf, vec_cmpeqv4si, 0, 0, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (s390_vceqg, vec_cmpeqv2di, 0, 0, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (s390_vfcedb, vec_cmpeqv2df, 0, 0, BT_FN_V2DI_V2DF_V2DF) + +OB_DEF (s390_vec_cmpge, s390_vec_cmpge_s8, s390_vec_cmpge_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cmpge_s8, vec_cmpgev16qi, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_cmpge_u8, vec_cmpgeuv16qi, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cmpge_s16, vec_cmpgev8hi, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_cmpge_u16, vec_cmpgeuv8hi, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cmpge_s32, vec_cmpgev4si, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_cmpge_u32, vec_cmpgeuv4si, 0, BT_OV_BV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cmpge_s64, vec_cmpgev2di, 0, BT_OV_BV2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_cmpge_u64, vec_cmpgeuv2di, 0, BT_OV_BV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_cmpge_dbl, s390_vfchedb, 0, BT_OV_BV2DI_V2DF_V2DF) + +B_DEF (vec_cmpgev16qi, vec_cmpgev16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmpgeuv16qi, vec_cmpgeuv16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmpgev8hi, vec_cmpgev8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmpgeuv8hi, vec_cmpgeuv8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmpgev4si, vec_cmpgev4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmpgeuv4si, vec_cmpgeuv4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmpgev2di, vec_cmpgev2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (vec_cmpgeuv2di, vec_cmpgeuv2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (s390_vfchedb, vec_cmpgev2df, 0, 0, BT_FN_V2DI_V2DF_V2DF) + +OB_DEF (s390_vec_cmpgt, s390_vec_cmpgt_s8, s390_vec_cmpgt_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cmpgt_s8, s390_vchb, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_cmpgt_u8, s390_vchlb, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cmpgt_s16, s390_vchh, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_cmpgt_u16, s390_vchlh, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cmpgt_s32, s390_vchf, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_cmpgt_u32, s390_vchlf, 0, BT_OV_BV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cmpgt_s64, s390_vchg, 0, BT_OV_BV2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_cmpgt_u64, s390_vchlg, 0, BT_OV_BV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_cmpgt_dbl, s390_vfchdb, 0, BT_OV_BV2DI_V2DF_V2DF) + +B_DEF (s390_vchb, vec_cmpgtv16qi, 0, 0, BT_FN_V16QI_V16QI_V16QI) +B_DEF (s390_vchlb, vec_cmpgtuv16qi, 0, 0, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (s390_vchh, vec_cmpgtv8hi, 0, 0, BT_FN_V8HI_V8HI_V8HI) +B_DEF (s390_vchlh, vec_cmpgtuv8hi, 0, 0, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (s390_vchf, vec_cmpgtv4si, 0, 0, BT_FN_V4SI_V4SI_V4SI) +B_DEF (s390_vchlf, vec_cmpgtuv4si, 0, 0, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (s390_vchg, vec_cmpgtv2di, 0, 0, BT_FN_V2DI_V2DI_V2DI) +B_DEF (s390_vchlg, vec_cmpgtuv2di, 0, 0, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (s390_vfchdb, vec_cmpgtv2df, 0, 0, BT_FN_V2DI_V2DF_V2DF) + +OB_DEF (s390_vec_cmple, s390_vec_cmple_s8, s390_vec_cmple_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cmple_s8, vec_cmplev16qi, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_cmple_u8, vec_cmpleuv16qi, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cmple_s16, vec_cmplev8hi, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_cmple_u16, vec_cmpleuv8hi, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cmple_s32, vec_cmplev4si, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_cmple_u32, vec_cmpleuv4si, 0, BT_OV_BV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cmple_s64, vec_cmplev2di, 0, BT_OV_BV2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_cmple_u64, vec_cmpleuv2di, 0, BT_OV_BV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_cmple_dbl, vec_cmplev2df, 0, BT_OV_BV2DI_V2DF_V2DF) + +B_DEF (vec_cmplev16qi, vec_cmplev16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmpleuv16qi, vec_cmpleuv16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmplev8hi, vec_cmplev8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmpleuv8hi, vec_cmpleuv8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmplev4si, vec_cmplev4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmpleuv4si, vec_cmpleuv4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmplev2di, vec_cmplev2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (vec_cmpleuv2di, vec_cmpleuv2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (vec_cmplev2df, vec_cmplev2df, 0, B_INT, BT_FN_V2DI_V2DF_V2DF) + +OB_DEF (s390_vec_cmplt, s390_vec_cmplt_s8, s390_vec_cmplt_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cmplt_s8, vec_cmpltv16qi, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_cmplt_u8, vec_cmpltuv16qi, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cmplt_s16, vec_cmpltv8hi, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_cmplt_u16, vec_cmpltuv8hi, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cmplt_s32, vec_cmpltv4si, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_cmplt_u32, vec_cmpltuv4si, 0, BT_OV_BV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cmplt_s64, vec_cmpltv2di, 0, BT_OV_BV2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_cmplt_u64, vec_cmpltuv2di, 0, BT_OV_BV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_cmplt_dbl, vec_cmpltv2df, 0, BT_OV_BV2DI_V2DF_V2DF) + +B_DEF (vec_cmpltv16qi, vec_cmpltv16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmpltuv16qi, vec_cmpltuv16qi, 0, B_INT, BT_FN_V16QI_UV16QI_UV16QI) +B_DEF (vec_cmpltv8hi, vec_cmpltv8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmpltuv8hi, vec_cmpltuv8hi, 0, B_INT, BT_FN_V8HI_UV8HI_UV8HI) +B_DEF (vec_cmpltv4si, vec_cmpltv4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmpltuv4si, vec_cmpltuv4si, 0, B_INT, BT_FN_V4SI_UV4SI_UV4SI) +B_DEF (vec_cmpltv2di, vec_cmpltv2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (vec_cmpltuv2di, vec_cmpltuv2di, 0, B_INT, BT_FN_V2DI_UV2DI_UV2DI) +B_DEF (vec_cmpltv2df, vec_cmpltv2df, 0, B_INT, BT_FN_V2DI_V2DF_V2DF) + +OB_DEF (s390_vec_cntlz, s390_vec_cntlz_s8, s390_vec_cntlz_u64, BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cntlz_s8, s390_vclzb, 0, BT_OV_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_cntlz_u8, s390_vclzb, 0, BT_OV_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cntlz_s16, s390_vclzh, 0, BT_OV_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_cntlz_u16, s390_vclzh, 0, BT_OV_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cntlz_s32, s390_vclzf, 0, BT_OV_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_cntlz_u32, s390_vclzf, 0, BT_OV_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cntlz_s64, s390_vclzg, 0, BT_OV_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_cntlz_u64, s390_vclzg, 0, BT_OV_UV2DI_UV2DI) + +B_DEF (s390_vclzb, clzv16qi2, 0, 0, BT_FN_UV16QI_UV16QI) +B_DEF (s390_vclzh, clzv8hi2, 0, 0, BT_FN_UV8HI_UV8HI) +B_DEF (s390_vclzf, clzv4si2, 0, 0, BT_FN_UV4SI_UV4SI) +B_DEF (s390_vclzg, clzv2di2, 0, 0, BT_FN_UV2DI_UV2DI) + +OB_DEF (s390_vec_cnttz, s390_vec_cnttz_s8, s390_vec_cnttz_u64, BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_cnttz_s8, s390_vctzb, 0, BT_OV_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_cnttz_u8, s390_vctzb, 0, BT_OV_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_cnttz_s16, s390_vctzh, 0, BT_OV_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_cnttz_u16, s390_vctzh, 0, BT_OV_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_cnttz_s32, s390_vctzf, 0, BT_OV_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_cnttz_u32, s390_vctzf, 0, BT_OV_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_cnttz_s64, s390_vctzg, 0, BT_OV_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_cnttz_u64, s390_vctzg, 0, BT_OV_UV2DI_UV2DI) + +B_DEF (s390_vctzb, ctzv16qi2, 0, 0, BT_FN_UV16QI_UV16QI) +B_DEF (s390_vctzh, ctzv8hi2, 0, 0, BT_FN_UV8HI_UV8HI) +B_DEF (s390_vctzf, ctzv4si2, 0, 0, BT_FN_UV4SI_UV4SI) +B_DEF (s390_vctzg, ctzv2di2, 0, 0, BT_FN_UV2DI_UV2DI) + +OB_DEF (s390_vec_xor, s390_vec_xor_b8, s390_vec_xor_dbl_c, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_xor_b8, s390_vx, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_xor_s8_a, s390_vx, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_xor_s8_b, s390_vx, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_xor_s8_c, s390_vx, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_xor_u8_a, s390_vx, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_xor_u8_b, s390_vx, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_xor_u8_c, s390_vx, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_xor_b16, s390_vx, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_xor_s16_a, s390_vx, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_xor_s16_b, s390_vx, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_xor_s16_c, s390_vx, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_xor_u16_a, s390_vx, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_xor_u16_b, s390_vx, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_xor_u16_c, s390_vx, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_xor_b32, s390_vx, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_xor_s32_a, s390_vx, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_xor_s32_b, s390_vx, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_xor_s32_c, s390_vx, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_xor_u32_a, s390_vx, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_xor_u32_b, s390_vx, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_xor_u32_c, s390_vx, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_xor_b64, s390_vx, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_xor_s64_a, s390_vx, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_xor_s64_b, s390_vx, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_xor_s64_c, s390_vx, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_xor_u64_a, s390_vx, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_xor_u64_b, s390_vx, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_xor_u64_c, s390_vx, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_xor_dbl_a, s390_vx, 0, BT_OV_V2DF_BV2DI_V2DF) +OB_DEF_VAR (s390_vec_xor_dbl_b, s390_vx, 0, BT_OV_V2DF_V2DF_V2DF) +OB_DEF_VAR (s390_vec_xor_dbl_c, s390_vx, 0, BT_OV_V2DF_V2DF_BV2DI) + +B_DEF (s390_vx, xorv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_gfmsum, s390_vec_gfmsum_u8, s390_vec_gfmsum_u32,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_gfmsum_u8, s390_vgfmb, 0, BT_OV_UV8HI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_gfmsum_u16, s390_vgfmh, 0, BT_OV_UV4SI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_gfmsum_u32, s390_vgfmf, 0, BT_OV_UV2DI_UV4SI_UV4SI) + +B_DEF (s390_vgfmb, vec_gfmsumv16qi, 0, 0, BT_FN_UV8HI_UV16QI_UV16QI) +B_DEF (s390_vgfmh, vec_gfmsumv8hi, 0, 0, BT_FN_UV4SI_UV8HI_UV8HI) +B_DEF (s390_vgfmf, vec_gfmsumv4si, 0, 0, BT_FN_UV2DI_UV4SI_UV4SI) +B_DEF (s390_vgfmg, vec_gfmsum_128, 0, 0, BT_FN_UV16QI_UV2DI_UV2DI) + +OB_DEF (s390_vec_gfmsum_accum, s390_vec_gfmsum_accum_u8,s390_vec_gfmsum_accum_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_gfmsum_accum_u8, s390_vgfmab, 0, BT_OV_UV8HI_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_gfmsum_accum_u16, s390_vgfmah, 0, BT_OV_UV4SI_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_gfmsum_accum_u32, s390_vgfmaf, 0, BT_OV_UV2DI_UV4SI_UV4SI_UV2DI) + +B_DEF (s390_vgfmab, vec_gfmsum_accumv16qi,0, 0, BT_FN_UV8HI_UV16QI_UV16QI_UV8HI) +B_DEF (s390_vgfmah, vec_gfmsum_accumv8hi,0, 0, BT_FN_UV4SI_UV8HI_UV8HI_UV4SI) +B_DEF (s390_vgfmaf, vec_gfmsum_accumv4si,0, 0, BT_FN_UV2DI_UV4SI_UV4SI_UV2DI) +B_DEF (s390_vgfmag, vec_gfmsum_accum_128,0, 0, BT_FN_UV16QI_UV2DI_UV2DI_UV16QI) + +OB_DEF (s390_vec_abs, s390_vec_abs_s8, s390_vec_abs_dbl, BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_abs_s8, s390_vlpb, 0, BT_OV_V16QI_V16QI) +OB_DEF_VAR (s390_vec_abs_s16, s390_vlph, 0, BT_OV_V8HI_V8HI) +OB_DEF_VAR (s390_vec_abs_s32, s390_vlpf, 0, BT_OV_V4SI_V4SI) +OB_DEF_VAR (s390_vec_abs_s64, s390_vlpg, 0, BT_OV_V2DI_V2DI) +OB_DEF_VAR (s390_vec_abs_dbl, s390_vflpdb, 0, BT_OV_V2DF_V2DF) + +B_DEF (s390_vlpb, absv16qi2, 0, 0, BT_FN_V16QI_V16QI) +B_DEF (s390_vlph, absv8hi2, 0, 0, BT_FN_V8HI_V8HI) +B_DEF (s390_vlpf, absv4si2, 0, 0, BT_FN_V4SI_V4SI) +B_DEF (s390_vlpg, absv2di2, 0, 0, BT_FN_V2DI_V2DI) +B_DEF (s390_vflpdb, absv2df2, 0, 0, BT_FN_V2DF_V2DF) + +OB_DEF (s390_vec_max, s390_vec_max_s8_a, s390_vec_max_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_max_s8_a, s390_vmxb, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_max_s8_b, s390_vmxb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_max_s8_c, s390_vmxb, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_max_u8_a, s390_vmxlb, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_max_u8_b, s390_vmxlb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_max_u8_c, s390_vmxlb, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_max_s16_a, s390_vmxh, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_max_s16_b, s390_vmxh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_max_s16_c, s390_vmxh, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_max_u16_a, s390_vmxlh, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_max_u16_b, s390_vmxlh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_max_u16_c, s390_vmxlh, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_max_s32_a, s390_vmxf, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_max_s32_b, s390_vmxf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_max_s32_c, s390_vmxf, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_max_u32_a, s390_vmxlf, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_max_u32_b, s390_vmxlf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_max_u32_c, s390_vmxlf, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_max_s64_a, s390_vmxg, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_max_s64_b, s390_vmxg, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_max_s64_c, s390_vmxg, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_max_u64_a, s390_vmxlg, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_max_u64_b, s390_vmxlg, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_max_u64_c, s390_vmxlg, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_max_dbl, s390_vec_max_dbl, 0, BT_OV_V2DF_V2DF_V2DF) + +B_DEF (s390_vmxb, smaxv16qi3, 0, 0, BT_FN_V16QI_BV16QI_V16QI) +B_DEF (s390_vmxlb, umaxv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmxh, smaxv8hi3, 0, 0, BT_FN_V8HI_BV8HI_V8HI) +B_DEF (s390_vmxlh, umaxv8hi3, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmxf, smaxv4si3, 0, 0, BT_FN_V4SI_BV4SI_V4SI) +B_DEF (s390_vmxlf, umaxv4si3, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmxg, smaxv2di3, 0, 0, BT_FN_V2DI_BV2DI_V2DI) +B_DEF (s390_vmxlg, umaxv2di3, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) +B_DEF (s390_vec_max_dbl, smaxv2df3, 0, B_INT, BT_FN_V2DF_V2DF_V2DF) + +OB_DEF (s390_vec_min, s390_vec_min_s8_a, s390_vec_min_dbl, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_min_s8_a, s390_vmnb, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_min_s8_b, s390_vmnb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_min_s8_c, s390_vmnb, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_min_u8_a, s390_vmnlb, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_min_u8_b, s390_vmnlb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_min_u8_c, s390_vmnlb, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_min_s16_a, s390_vmnh, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_min_s16_b, s390_vmnh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_min_s16_c, s390_vmnh, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_min_u16_a, s390_vmnlh, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_min_u16_b, s390_vmnlh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_min_u16_c, s390_vmnlh, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_min_s32_a, s390_vmnf, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_min_s32_b, s390_vmnf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_min_s32_c, s390_vmnf, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_min_u32_a, s390_vmnlf, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_min_u32_b, s390_vmnlf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_min_u32_c, s390_vmnlf, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_min_s64_a, s390_vmng, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_min_s64_b, s390_vmng, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_min_s64_c, s390_vmng, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_min_u64_a, s390_vmnlg, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_min_u64_b, s390_vmnlg, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_min_u64_c, s390_vmnlg, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_min_dbl, s390_vec_min_dbl, 0, BT_OV_V2DF_V2DF_V2DF) + +B_DEF (s390_vmnb, sminv16qi3, 0, 0, BT_FN_V16QI_BV16QI_V16QI) +B_DEF (s390_vmnlb, uminv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmnh, sminv8hi3, 0, 0, BT_FN_V8HI_BV8HI_V8HI) +B_DEF (s390_vmnlh, uminv8hi3, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmnf, sminv4si3, 0, 0, BT_FN_V4SI_BV4SI_V4SI) +B_DEF (s390_vmnlf, uminv4si3, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmng, sminv2di3, 0, 0, BT_FN_V2DI_BV2DI_V2DI) +B_DEF (s390_vmnlg, uminv2di3, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) +B_DEF (s390_vec_min_dbl, sminv2df3, 0, B_INT, BT_FN_V2DF_V2DF_V2DF) + +OB_DEF (s390_vec_mladd, s390_vec_mladd_u8, s390_vec_mladd_s32_c,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mladd_u8, s390_vmalb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mladd_s8_a, s390_vmalb, 0, BT_OV_V16QI_UV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mladd_s8_b, s390_vmalb, 0, BT_OV_V16QI_V16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mladd_s8_c, s390_vmalb, 0, BT_OV_V16QI_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mladd_u16, s390_vmalhw, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mladd_s16_a, s390_vmalhw, 0, BT_OV_V8HI_UV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mladd_s16_b, s390_vmalhw, 0, BT_OV_V8HI_V8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mladd_s16_c, s390_vmalhw, 0, BT_OV_V8HI_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mladd_u32, s390_vmalf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mladd_s32_a, s390_vmalf, 0, BT_OV_V4SI_UV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_mladd_s32_b, s390_vmalf, 0, BT_OV_V4SI_V4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mladd_s32_c, s390_vmalf, 0, BT_OV_V4SI_V4SI_V4SI_V4SI) + +B_DEF (s390_vmalb, vec_vmalv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmalhw, vec_vmalv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmalf, vec_vmalv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_mhadd, s390_vec_mhadd_u8, s390_vec_mhadd_s32, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mhadd_u8, s390_vmalhb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mhadd_s8, s390_vmahb, 0, BT_OV_V16QI_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mhadd_u16, s390_vmalhh, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mhadd_s16, s390_vmahh, 0, BT_OV_V8HI_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mhadd_u32, s390_vmalhf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mhadd_s32, s390_vmahf, 0, BT_OV_V4SI_V4SI_V4SI_V4SI) + +B_DEF (s390_vmalhb, vec_vmalhv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmahb, vec_vmahv16qi, 0, 0, BT_FN_V16QI_V16QI_V16QI_V16QI) +B_DEF (s390_vmalhh, vec_vmalhv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmahh, vec_vmahv8hi, 0, 0, BT_FN_V8HI_V8HI_V8HI_V8HI) +B_DEF (s390_vmalhf, vec_vmalhv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmahf, vec_vmahv4si, 0, 0, BT_FN_V4SI_V4SI_V4SI_V4SI) + +OB_DEF (s390_vec_meadd, s390_vec_meadd_u8, s390_vec_meadd_s32, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_meadd_u8, s390_vmaleb, 0, BT_OV_UV8HI_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_meadd_s8, s390_vmaeb, 0, BT_OV_V8HI_V16QI_V16QI_V8HI) +OB_DEF_VAR (s390_vec_meadd_u16, s390_vmaleh, 0, BT_OV_UV4SI_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_meadd_s16, s390_vmaeh, 0, BT_OV_V4SI_V8HI_V8HI_V4SI) +OB_DEF_VAR (s390_vec_meadd_u32, s390_vmalef, 0, BT_OV_UV2DI_UV4SI_UV4SI_UV2DI) +OB_DEF_VAR (s390_vec_meadd_s32, s390_vmaef, 0, BT_OV_V2DI_V4SI_V4SI_V2DI) + +B_DEF (s390_vmaleb, vec_vmalev16qi, 0, 0, BT_FN_UV8HI_UV16QI_UV16QI_UV8HI) +B_DEF (s390_vmaeb, vec_vmaev16qi, 0, 0, BT_FN_V8HI_V16QI_V16QI_V8HI) +B_DEF (s390_vmaleh, vec_vmalev8hi, 0, 0, BT_FN_UV4SI_UV8HI_UV8HI_UV4SI) +B_DEF (s390_vmaeh, vec_vmaev8hi, 0, 0, BT_FN_V4SI_V8HI_V8HI_V4SI) +B_DEF (s390_vmalef, vec_vmalev4si, 0, 0, BT_FN_UV2DI_UV4SI_UV4SI_UV2DI) +B_DEF (s390_vmaef, vec_vmaev4si, 0, 0, BT_FN_V2DI_V4SI_V4SI_V2DI) + +OB_DEF (s390_vec_moadd, s390_vec_moadd_u8, s390_vec_moadd_s32, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_moadd_u8, s390_vmalob, 0, BT_OV_UV8HI_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_moadd_s8, s390_vmaob, 0, BT_OV_V8HI_V16QI_V16QI_V8HI) +OB_DEF_VAR (s390_vec_moadd_u16, s390_vmaloh, 0, BT_OV_UV4SI_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_moadd_s16, s390_vmaoh, 0, BT_OV_V4SI_V8HI_V8HI_V4SI) +OB_DEF_VAR (s390_vec_moadd_u32, s390_vmalof, 0, BT_OV_UV2DI_UV4SI_UV4SI_UV2DI) +OB_DEF_VAR (s390_vec_moadd_s32, s390_vmaof, 0, BT_OV_V2DI_V4SI_V4SI_V2DI) + +B_DEF (s390_vmalob, vec_vmalov16qi, 0, 0, BT_FN_UV8HI_UV16QI_UV16QI_UV8HI) +B_DEF (s390_vmaob, vec_vmaov16qi, 0, 0, BT_FN_V8HI_V16QI_V16QI_V8HI) +B_DEF (s390_vmaloh, vec_vmalov8hi, 0, 0, BT_FN_UV4SI_UV8HI_UV8HI_UV4SI) +B_DEF (s390_vmaoh, vec_vmaov8hi, 0, 0, BT_FN_V4SI_V8HI_V8HI_V4SI) +B_DEF (s390_vmalof, vec_vmalov4si, 0, 0, BT_FN_UV2DI_UV4SI_UV4SI_UV2DI) +B_DEF (s390_vmaof, vec_vmaov4si, 0, 0, BT_FN_V2DI_V4SI_V4SI_V2DI) + +OB_DEF (s390_vec_mulh, s390_vec_mulh_u8, s390_vec_mulh_s32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mulh_u8, s390_vmlhb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mulh_s8, s390_vmhb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mulh_u16, s390_vmlhh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mulh_s16, s390_vmhh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mulh_u32, s390_vmlhf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mulh_s32, s390_vmhf, 0, BT_OV_V4SI_V4SI_V4SI) + +B_DEF (s390_vmlhb, vec_umulhv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vmhb, vec_smulhv16qi, 0, 0, BT_FN_V16QI_V16QI_V16QI) +B_DEF (s390_vmlhh, vec_umulhv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vmhh, vec_smulhv8hi, 0, 0, BT_FN_V8HI_V8HI_V8HI) +B_DEF (s390_vmlhf, vec_umulhv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vmhf, vec_smulhv4si, 0, 0, BT_FN_V4SI_V4SI_V4SI) + +OB_DEF (s390_vec_mule, s390_vec_mule_u8, s390_vec_mule_s32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mule_u8, s390_vmleb, 0, BT_OV_UV8HI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mule_s8, s390_vmeb, 0, BT_OV_V8HI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mule_u16, s390_vmleh, 0, BT_OV_UV4SI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mule_s15, s390_vmeh, 0, BT_OV_V4SI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mule_u32, s390_vmlef, 0, BT_OV_UV2DI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mule_s32, s390_vmef, 0, BT_OV_V2DI_V4SI_V4SI) + +B_DEF (s390_vmleb, vec_widen_umult_even_v16qi,0, 0, BT_FN_UV8HI_UV16QI_UV16QI) +B_DEF (s390_vmeb, vec_widen_smult_even_v16qi,0, 0, BT_FN_V8HI_V16QI_V16QI) +B_DEF (s390_vmleh, vec_widen_umult_even_v8hi,0, 0, BT_FN_UV4SI_UV8HI_UV8HI) +B_DEF (s390_vmeh, vec_widen_smult_even_v8hi,0, 0, BT_FN_V4SI_V8HI_V8HI) +B_DEF (s390_vmlef, vec_widen_umult_even_v4si,0, 0, BT_FN_UV2DI_UV4SI_UV4SI) +B_DEF (s390_vmef, vec_widen_smult_even_v4si,0, 0, BT_FN_V2DI_V4SI_V4SI) + +OB_DEF (s390_vec_mulo, s390_vec_mulo_u8, s390_vec_mulo_s32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_mulo_u8, s390_vmlob, 0, BT_OV_UV8HI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_mulo_s8, s390_vmob, 0, BT_OV_V8HI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_mulo_u16, s390_vmloh, 0, BT_OV_UV4SI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_mulo_s16, s390_vmoh, 0, BT_OV_V4SI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_mulo_u32, s390_vmlof, 0, BT_OV_UV2DI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_mulo_s32, s390_vmof, 0, BT_OV_V2DI_V4SI_V4SI) + +B_DEF (s390_vmlob, vec_widen_umult_odd_v16qi,0, 0, BT_FN_UV8HI_UV16QI_UV16QI) +B_DEF (s390_vmob, vec_widen_smult_odd_v16qi,0, 0, BT_FN_V8HI_V16QI_V16QI) +B_DEF (s390_vmloh, vec_widen_umult_odd_v8hi,0, 0, BT_FN_UV4SI_UV8HI_UV8HI) +B_DEF (s390_vmoh, vec_widen_smult_odd_v8hi,0, 0, BT_FN_V4SI_V8HI_V8HI) +B_DEF (s390_vmlof, vec_widen_umult_odd_v4si,0, 0, BT_FN_UV2DI_UV4SI_UV4SI) +B_DEF (s390_vmof, vec_widen_smult_odd_v4si,0, 0, BT_FN_V2DI_V4SI_V4SI) + +OB_DEF (s390_vec_nor, s390_vec_nor_b8, s390_vec_nor_dbl_c, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_nor_b8, s390_vno, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_nor_s8_a, s390_vno, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_nor_s8_b, s390_vno, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_nor_s8_c, s390_vno, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_nor_u8_a, s390_vno, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_nor_u8_b, s390_vno, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_nor_u8_c, s390_vno, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_nor_b16, s390_vno, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_nor_s16_a, s390_vno, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_nor_s16_b, s390_vno, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_nor_s16_c, s390_vno, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_nor_u16_a, s390_vno, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_nor_u16_b, s390_vno, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_nor_u16_c, s390_vno, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_nor_b32, s390_vno, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_nor_s32_a, s390_vno, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_nor_s32_b, s390_vno, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_nor_s32_c, s390_vno, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_nor_u32_a, s390_vno, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_nor_u32_b, s390_vno, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_nor_u32_c, s390_vno, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_nor_b64, s390_vno, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_nor_s64_a, s390_vno, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_nor_s64_b, s390_vno, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_nor_s64_c, s390_vno, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_nor_u64_a, s390_vno, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_nor_u64_b, s390_vno, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_nor_u64_c, s390_vno, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_nor_dbl_a, s390_vno, 0, BT_OV_V2DF_BV2DI_V2DF) +OB_DEF_VAR (s390_vec_nor_dbl_b, s390_vno, 0, BT_OV_V2DF_V2DF_V2DF) +OB_DEF_VAR (s390_vec_nor_dbl_c, s390_vno, 0, BT_OV_V2DF_V2DF_BV2DI) + +B_DEF (s390_vno, vec_norv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_or, s390_vec_or_b8, s390_vec_or_dbl_c, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_or_b8, s390_vo, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vec_or_s8_a, s390_vo, 0, BT_OV_V16QI_BV16QI_V16QI) +OB_DEF_VAR (s390_vec_or_s8_b, s390_vo, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_or_s8_c, s390_vo, 0, BT_OV_V16QI_V16QI_BV16QI) +OB_DEF_VAR (s390_vec_or_u8_a, s390_vo, 0, BT_OV_UV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_or_u8_b, s390_vo, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_or_u8_c, s390_vo, 0, BT_OV_UV16QI_UV16QI_BV16QI) +OB_DEF_VAR (s390_vec_or_b16, s390_vo, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vec_or_s16_a, s390_vo, 0, BT_OV_V8HI_BV8HI_V8HI) +OB_DEF_VAR (s390_vec_or_s16_b, s390_vo, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_or_s16_c, s390_vo, 0, BT_OV_V8HI_V8HI_BV8HI) +OB_DEF_VAR (s390_vec_or_u16_a, s390_vo, 0, BT_OV_UV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_or_u16_b, s390_vo, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_or_u16_c, s390_vo, 0, BT_OV_UV8HI_UV8HI_BV8HI) +OB_DEF_VAR (s390_vec_or_b32, s390_vo, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vec_or_s32_a, s390_vo, 0, BT_OV_V4SI_BV4SI_V4SI) +OB_DEF_VAR (s390_vec_or_s32_b, s390_vo, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_or_s32_c, s390_vo, 0, BT_OV_V4SI_V4SI_BV4SI) +OB_DEF_VAR (s390_vec_or_u32_a, s390_vo, 0, BT_OV_UV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_or_u32_b, s390_vo, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_or_u32_c, s390_vo, 0, BT_OV_UV4SI_UV4SI_BV4SI) +OB_DEF_VAR (s390_vec_or_b64, s390_vo, 0, BT_OV_BV2DI_BV2DI_BV2DI) +OB_DEF_VAR (s390_vec_or_s64_a, s390_vo, 0, BT_OV_V2DI_BV2DI_V2DI) +OB_DEF_VAR (s390_vec_or_s64_b, s390_vo, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_or_s64_c, s390_vo, 0, BT_OV_V2DI_V2DI_BV2DI) +OB_DEF_VAR (s390_vec_or_u64_a, s390_vo, 0, BT_OV_UV2DI_BV2DI_UV2DI) +OB_DEF_VAR (s390_vec_or_u64_b, s390_vo, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_or_u64_c, s390_vo, 0, BT_OV_UV2DI_UV2DI_BV2DI) +OB_DEF_VAR (s390_vec_or_dbl_a, s390_vo, 0, BT_OV_V2DF_BV2DI_V2DF) +OB_DEF_VAR (s390_vec_or_dbl_b, s390_vo, 0, BT_OV_V2DF_V2DF_V2DF) +OB_DEF_VAR (s390_vec_or_dbl_c, s390_vo, 0, BT_OV_V2DF_V2DF_BV2DI) + +B_DEF (s390_vo, iorv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_popcnt, s390_vec_popcnt_s8, s390_vec_popcnt_u64,BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_popcnt_s8, s390_vpopctb, 0, BT_OV_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_popcnt_u8, s390_vpopctb, 0, BT_OV_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_popcnt_s16, s390_vpopcth, 0, BT_OV_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_popcnt_u16, s390_vpopcth, 0, BT_OV_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_popcnt_s32, s390_vpopctf, 0, BT_OV_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_popcnt_u32, s390_vpopctf, 0, BT_OV_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_popcnt_s64, s390_vpopctg, 0, BT_OV_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_popcnt_u64, s390_vpopctg, 0, BT_OV_UV2DI_UV2DI) + +B_DEF (s390_vpopctb, popcountv16qi2, 0, 0, BT_FN_UV16QI_UV16QI) +B_DEF (s390_vpopcth, popcountv8hi2, 0, 0, BT_FN_UV8HI_UV8HI) +B_DEF (s390_vpopctf, popcountv4si2, 0, 0, BT_FN_UV4SI_UV4SI) +B_DEF (s390_vpopctg, popcountv2di2, 0, 0, BT_FN_UV2DI_UV2DI) + +OB_DEF (s390_vec_rl, s390_vec_rl_u8, s390_vec_rl_s64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_rl_u8, s390_verllvb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_rl_s8, s390_verllvb, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_rl_u16, s390_verllvh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_rl_s16, s390_verllvh, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_rl_u32, s390_verllvf, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_rl_s32, s390_verllvf, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_rl_u64, s390_verllvg, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_rl_s64, s390_verllvg, 0, BT_OV_V2DI_V2DI_UV2DI) + +B_DEF (s390_verllvb, vrotlv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_verllvh, vrotlv8hi3, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_verllvf, vrotlv4si3, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_verllvg, vrotlv2di3, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) + +OB_DEF (s390_vec_rli, s390_vec_rli_u8, s390_vec_rli_s64, BT_FN_OV4SI_OV4SI_ULONG) +OB_DEF_VAR (s390_vec_rli_u8, s390_verllb, 0, BT_OV_UV16QI_UV16QI_ULONG) +OB_DEF_VAR (s390_vec_rli_s8, s390_verllb, 0, BT_OV_V16QI_V16QI_ULONG) +OB_DEF_VAR (s390_vec_rli_u16, s390_verllh, 0, BT_OV_UV8HI_UV8HI_ULONG) +OB_DEF_VAR (s390_vec_rli_s16, s390_verllh, 0, BT_OV_V8HI_V8HI_ULONG) +OB_DEF_VAR (s390_vec_rli_u32, s390_verllf, 0, BT_OV_UV4SI_UV4SI_ULONG) +OB_DEF_VAR (s390_vec_rli_s32, s390_verllf, 0, BT_OV_V4SI_V4SI_ULONG) +OB_DEF_VAR (s390_vec_rli_u64, s390_verllg, 0, BT_OV_UV2DI_UV2DI_ULONG) +OB_DEF_VAR (s390_vec_rli_s64, s390_verllg, 0, BT_OV_V2DI_V2DI_ULONG) + +B_DEF (s390_verllb, rotlv16qi3, 0, 0, BT_FN_UV16QI_UV16QI_UINT) +B_DEF (s390_verllh, rotlv8hi3, 0, 0, BT_FN_UV8HI_UV8HI_UINT) +B_DEF (s390_verllf, rotlv4si3, 0, 0, BT_FN_UV4SI_UV4SI_UINT) +B_DEF (s390_verllg, rotlv2di3, 0, 0, BT_FN_UV2DI_UV2DI_UINT) + +OB_DEF (s390_vec_rl_mask, s390_vec_rl_mask_s8,s390_vec_rl_mask_u64,BT_FN_OV4SI_OV4SI_OV4SI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_s8, s390_verimb, O3_U8, BT_OV_V16QI_V16QI_UV16QI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_u8, s390_verimb, O3_U8, BT_OV_UV16QI_UV16QI_UV16QI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_s16, s390_verimh, O3_U8, BT_OV_V8HI_V8HI_UV8HI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_u16, s390_verimh, O3_U8, BT_OV_UV8HI_UV8HI_UV8HI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_s32, s390_verimf, O3_U8, BT_OV_V4SI_V4SI_UV4SI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_u32, s390_verimf, O3_U8, BT_OV_UV4SI_UV4SI_UV4SI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_s64, s390_verimg, O3_U8, BT_OV_V2DI_V2DI_UV2DI_UCHAR) +OB_DEF_VAR (s390_vec_rl_mask_u64, s390_verimg, O3_U8, BT_OV_UV2DI_UV2DI_UV2DI_UCHAR) + +B_DEF (s390_verimb, verimv16qi, 0, O4_U8, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT) +B_DEF (s390_verimh, verimv8hi, 0, O4_U8, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT) +B_DEF (s390_verimf, verimv4si, 0, O4_U8, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT) +B_DEF (s390_verimg, verimv2di, 0, O4_U8, BT_FN_UV2DI_UV2DI_UV2DI_UV2DI_INT) + +OB_DEF (s390_vec_sll, s390_vec_sll_u8q, s390_vec_sll_b64s, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sll_u8q, s390_vsl, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sll_u8h, s390_vsl, 0, BT_OV_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_sll_u8s, s390_vsl, 0, BT_OV_UV16QI_UV16QI_UV4SI) +OB_DEF_VAR (s390_vec_sll_s8q, s390_vsl, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_sll_s8h, s390_vsl, 0, BT_OV_V16QI_V16QI_UV8HI) +OB_DEF_VAR (s390_vec_sll_s8s, s390_vsl, 0, BT_OV_V16QI_V16QI_UV4SI) +OB_DEF_VAR (s390_vec_sll_b8q, s390_vsl, 0, BT_OV_BV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sll_b8h, s390_vsl, 0, BT_OV_BV16QI_BV16QI_UV8HI) +OB_DEF_VAR (s390_vec_sll_b8s, s390_vsl, 0, BT_OV_BV16QI_BV16QI_UV4SI) +OB_DEF_VAR (s390_vec_sll_u16q, s390_vsl, 0, BT_OV_UV8HI_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_sll_u16h, s390_vsl, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sll_u16s, s390_vsl, 0, BT_OV_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_sll_s16q, s390_vsl, 0, BT_OV_V8HI_V8HI_UV16QI) +OB_DEF_VAR (s390_vec_sll_s16h, s390_vsl, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_sll_s16s, s390_vsl, 0, BT_OV_V8HI_V8HI_UV4SI) +OB_DEF_VAR (s390_vec_sll_b16q, s390_vsl, 0, BT_OV_BV8HI_BV8HI_UV16QI) +OB_DEF_VAR (s390_vec_sll_b16h, s390_vsl, 0, BT_OV_BV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sll_b16s, s390_vsl, 0, BT_OV_BV8HI_BV8HI_UV4SI) +OB_DEF_VAR (s390_vec_sll_u32q, s390_vsl, 0, BT_OV_UV4SI_UV4SI_UV16QI) +OB_DEF_VAR (s390_vec_sll_u32h, s390_vsl, 0, BT_OV_UV4SI_UV4SI_UV8HI) +OB_DEF_VAR (s390_vec_sll_u32s, s390_vsl, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sll_s32q, s390_vsl, 0, BT_OV_V4SI_V4SI_UV16QI) +OB_DEF_VAR (s390_vec_sll_s32h, s390_vsl, 0, BT_OV_V4SI_V4SI_UV8HI) +OB_DEF_VAR (s390_vec_sll_s32s, s390_vsl, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_sll_b32q, s390_vsl, 0, BT_OV_BV4SI_BV4SI_UV16QI) +OB_DEF_VAR (s390_vec_sll_b32h, s390_vsl, 0, BT_OV_BV4SI_BV4SI_UV8HI) +OB_DEF_VAR (s390_vec_sll_b32s, s390_vsl, 0, BT_OV_BV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sll_u64q, s390_vsl, 0, BT_OV_UV2DI_UV2DI_UV16QI) +OB_DEF_VAR (s390_vec_sll_u64h, s390_vsl, 0, BT_OV_UV2DI_UV2DI_UV8HI) +OB_DEF_VAR (s390_vec_sll_u64s, s390_vsl, 0, BT_OV_UV2DI_UV2DI_UV4SI) +OB_DEF_VAR (s390_vec_sll_s64q, s390_vsl, 0, BT_OV_V2DI_V2DI_UV16QI) +OB_DEF_VAR (s390_vec_sll_s64h, s390_vsl, 0, BT_OV_V2DI_V2DI_UV8HI) +OB_DEF_VAR (s390_vec_sll_s64s, s390_vsl, 0, BT_OV_V2DI_V2DI_UV4SI) +OB_DEF_VAR (s390_vec_sll_b64q, s390_vsl, 0, BT_OV_BV2DI_BV2DI_UV16QI) +OB_DEF_VAR (s390_vec_sll_b64h, s390_vsl, 0, BT_OV_BV2DI_BV2DI_UV8HI) +OB_DEF_VAR (s390_vec_sll_b64s, s390_vsl, 0, BT_OV_BV2DI_BV2DI_UV4SI) + +B_DEF (s390_vsl, vec_sllv16qiv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_slb, s390_vec_slb_u8_u8, s390_vec_slb_dbl_s64,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_slb_u8_u8, s390_vslb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_slb_u8_s8, s390_vslb, 0, BT_OV_UV16QI_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_slb_s8_u8, s390_vslb, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_slb_s8_s8, s390_vslb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_slb_u16_u16, s390_vslb, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_slb_u16_s16, s390_vslb, 0, BT_OV_UV8HI_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_slb_s16_u16, s390_vslb, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_slb_s16_s16, s390_vslb, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_slb_u32_u32, s390_vslb, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_slb_u32_s32, s390_vslb, 0, BT_OV_UV4SI_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_slb_s32_u32, s390_vslb, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_slb_s32_s32, s390_vslb, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_slb_u64_u64, s390_vslb, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_slb_u64_s64, s390_vslb, 0, BT_OV_UV2DI_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_slb_s64_u64, s390_vslb, 0, BT_OV_V2DI_V2DI_UV2DI) +OB_DEF_VAR (s390_vec_slb_s64_s64, s390_vslb, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_slb_dbl_u64, s390_vslb, 0, BT_OV_V2DF_V2DF_UV2DI) +OB_DEF_VAR (s390_vec_slb_dbl_s64, s390_vslb, 0, BT_OV_V2DF_V2DF_V2DI) + +B_DEF (s390_vslb, vec_slbv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_sld, s390_vec_sld_s8, s390_vec_sld_dbl, BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_s8, s390_vsldb, O3_U4, BT_OV_V16QI_V16QI_V16QI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_u8, s390_vsldb, O3_U4, BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_s16, s390_vsldb, O3_U4, BT_OV_V8HI_V8HI_V8HI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_u16, s390_vsldb, O3_U4, BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_s32, s390_vsldb, O3_U4, BT_OV_V4SI_V4SI_V4SI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_u32, s390_vsldb, O3_U4, BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_s64, s390_vsldb, O3_U4, BT_OV_V2DI_V2DI_V2DI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_u64, s390_vsldb, O3_U4, BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG) +OB_DEF_VAR (s390_vec_sld_dbl, s390_vsldb, O3_U4, BT_OV_V2DF_V2DF_V2DF_ULONGLONG) + +B_DEF (s390_vsldb, vec_sldv16qi, 0, O3_U4, BT_FN_UV16QI_UV16QI_UV16QI_INT) + +OB_DEF (s390_vec_sldw, s390_vec_sldw_s8, s390_vec_sldw_dbl, BT_FN_OV4SI_OV4SI_OV4SI_INT) +OB_DEF_VAR (s390_vec_sldw_s8, s390_vsldb, O3_U4, BT_OV_V16QI_V16QI_V16QI_INT) +OB_DEF_VAR (s390_vec_sldw_u8, s390_vsldb, O3_U4, BT_OV_UV16QI_UV16QI_UV16QI_INT) +OB_DEF_VAR (s390_vec_sldw_s16, s390_vsldb, O3_U4, BT_OV_V8HI_V8HI_V8HI_INT) +OB_DEF_VAR (s390_vec_sldw_u16, s390_vsldb, O3_U4, BT_OV_UV8HI_UV8HI_UV8HI_INT) +OB_DEF_VAR (s390_vec_sldw_s32, s390_vsldb, O3_U4, BT_OV_V4SI_V4SI_V4SI_INT) +OB_DEF_VAR (s390_vec_sldw_u32, s390_vsldb, O3_U4, BT_OV_UV4SI_UV4SI_UV4SI_INT) +OB_DEF_VAR (s390_vec_sldw_s64, s390_vsldb, O3_U4, BT_OV_V2DI_V2DI_V2DI_INT) +OB_DEF_VAR (s390_vec_sldw_u64, s390_vsldb, O3_U4, BT_OV_UV2DI_UV2DI_UV2DI_INT) +OB_DEF_VAR (s390_vec_sldw_dbl, s390_vsldb, O3_U4, BT_OV_V2DF_V2DF_V2DF_INT) + +OB_DEF (s390_vec_sral, s390_vec_sral_u8q, s390_vec_sral_b64s, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sral_u8q, s390_vsra, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sral_u8h, s390_vsra, 0, BT_OV_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_sral_u8s, s390_vsra, 0, BT_OV_UV16QI_UV16QI_UV4SI) +OB_DEF_VAR (s390_vec_sral_s8q, s390_vsra, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_sral_s8h, s390_vsra, 0, BT_OV_V16QI_V16QI_UV8HI) +OB_DEF_VAR (s390_vec_sral_s8s, s390_vsra, 0, BT_OV_V16QI_V16QI_UV4SI) +OB_DEF_VAR (s390_vec_sral_b8q, s390_vsra, 0, BT_OV_BV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sral_b8h, s390_vsra, 0, BT_OV_BV16QI_BV16QI_UV8HI) +OB_DEF_VAR (s390_vec_sral_b8s, s390_vsra, 0, BT_OV_BV16QI_BV16QI_UV4SI) +OB_DEF_VAR (s390_vec_sral_u16q, s390_vsra, 0, BT_OV_UV8HI_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_sral_u16h, s390_vsra, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sral_u16s, s390_vsra, 0, BT_OV_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_sral_s16q, s390_vsra, 0, BT_OV_V8HI_V8HI_UV16QI) +OB_DEF_VAR (s390_vec_sral_s16h, s390_vsra, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_sral_s16s, s390_vsra, 0, BT_OV_V8HI_V8HI_UV4SI) +OB_DEF_VAR (s390_vec_sral_b16q, s390_vsra, 0, BT_OV_BV8HI_BV8HI_UV16QI) +OB_DEF_VAR (s390_vec_sral_b16h, s390_vsra, 0, BT_OV_BV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sral_b16s, s390_vsra, 0, BT_OV_BV8HI_BV8HI_UV4SI) +OB_DEF_VAR (s390_vec_sral_u32q, s390_vsra, 0, BT_OV_UV4SI_UV4SI_UV16QI) +OB_DEF_VAR (s390_vec_sral_u32h, s390_vsra, 0, BT_OV_UV4SI_UV4SI_UV8HI) +OB_DEF_VAR (s390_vec_sral_u32s, s390_vsra, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sral_s32q, s390_vsra, 0, BT_OV_V4SI_V4SI_UV16QI) +OB_DEF_VAR (s390_vec_sral_s32h, s390_vsra, 0, BT_OV_V4SI_V4SI_UV8HI) +OB_DEF_VAR (s390_vec_sral_s32s, s390_vsra, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_sral_b32q, s390_vsra, 0, BT_OV_BV4SI_BV4SI_UV16QI) +OB_DEF_VAR (s390_vec_sral_b32h, s390_vsra, 0, BT_OV_BV4SI_BV4SI_UV8HI) +OB_DEF_VAR (s390_vec_sral_b32s, s390_vsra, 0, BT_OV_BV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sral_u64q, s390_vsra, 0, BT_OV_UV2DI_UV2DI_UV16QI) +OB_DEF_VAR (s390_vec_sral_u64h, s390_vsra, 0, BT_OV_UV2DI_UV2DI_UV8HI) +OB_DEF_VAR (s390_vec_sral_u64s, s390_vsra, 0, BT_OV_UV2DI_UV2DI_UV4SI) +OB_DEF_VAR (s390_vec_sral_s64q, s390_vsra, 0, BT_OV_V2DI_V2DI_UV16QI) +OB_DEF_VAR (s390_vec_sral_s64h, s390_vsra, 0, BT_OV_V2DI_V2DI_UV8HI) +OB_DEF_VAR (s390_vec_sral_s64s, s390_vsra, 0, BT_OV_V2DI_V2DI_UV4SI) +OB_DEF_VAR (s390_vec_sral_b64q, s390_vsra, 0, BT_OV_BV2DI_BV2DI_UV16QI) +OB_DEF_VAR (s390_vec_sral_b64h, s390_vsra, 0, BT_OV_BV2DI_BV2DI_UV8HI) +OB_DEF_VAR (s390_vec_sral_b64s, s390_vsra, 0, BT_OV_BV2DI_BV2DI_UV4SI) + +B_DEF (s390_vsra, vec_sralv16qiv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_srab, s390_vec_srab_u8_u8,s390_vec_srab_dbl_s64,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_srab_u8_u8, s390_vsrab, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_srab_u8_s8, s390_vsrab, 0, BT_OV_UV16QI_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_srab_s8_u8, s390_vsrab, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_srab_s8_s8, s390_vsrab, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_srab_u16_u16, s390_vsrab, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_srab_u16_s16, s390_vsrab, 0, BT_OV_UV8HI_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_srab_s16_u16, s390_vsrab, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_srab_s16_s16, s390_vsrab, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_srab_u32_u32, s390_vsrab, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_srab_u32_s32, s390_vsrab, 0, BT_OV_UV4SI_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_srab_s32_u32, s390_vsrab, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_srab_s32_s32, s390_vsrab, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_srab_u64_u64, s390_vsrab, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_srab_u64_s64, s390_vsrab, 0, BT_OV_UV2DI_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_srab_s64_u64, s390_vsrab, 0, BT_OV_V2DI_V2DI_UV2DI) +OB_DEF_VAR (s390_vec_srab_s64_s64, s390_vsrab, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_srab_dbl_u64, s390_vsrab, 0, BT_OV_V2DF_V2DF_UV2DI) +OB_DEF_VAR (s390_vec_srab_dbl_s64, s390_vsrab, 0, BT_OV_V2DF_V2DF_V2DI) + +B_DEF (s390_vsrab, vec_srabv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_srl, s390_vec_srl_u8q, s390_vec_srl_b64s, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_srl_u8q, s390_vsrl, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_srl_u8h, s390_vsrl, 0, BT_OV_UV16QI_UV16QI_UV8HI) +OB_DEF_VAR (s390_vec_srl_u8s, s390_vsrl, 0, BT_OV_UV16QI_UV16QI_UV4SI) +OB_DEF_VAR (s390_vec_srl_s8q, s390_vsrl, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_srl_s8h, s390_vsrl, 0, BT_OV_V16QI_V16QI_UV8HI) +OB_DEF_VAR (s390_vec_srl_s8s, s390_vsrl, 0, BT_OV_V16QI_V16QI_UV4SI) +OB_DEF_VAR (s390_vec_srl_b8q, s390_vsrl, 0, BT_OV_BV16QI_BV16QI_UV16QI) +OB_DEF_VAR (s390_vec_srl_b8h, s390_vsrl, 0, BT_OV_BV16QI_BV16QI_UV8HI) +OB_DEF_VAR (s390_vec_srl_b8s, s390_vsrl, 0, BT_OV_BV16QI_BV16QI_UV4SI) +OB_DEF_VAR (s390_vec_srl_u16q, s390_vsrl, 0, BT_OV_UV8HI_UV8HI_UV16QI) +OB_DEF_VAR (s390_vec_srl_u16h, s390_vsrl, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_srl_u16s, s390_vsrl, 0, BT_OV_UV8HI_UV8HI_UV4SI) +OB_DEF_VAR (s390_vec_srl_s16q, s390_vsrl, 0, BT_OV_V8HI_V8HI_UV16QI) +OB_DEF_VAR (s390_vec_srl_s16h, s390_vsrl, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_srl_s16s, s390_vsrl, 0, BT_OV_V8HI_V8HI_UV4SI) +OB_DEF_VAR (s390_vec_srl_b16q, s390_vsrl, 0, BT_OV_BV8HI_BV8HI_UV16QI) +OB_DEF_VAR (s390_vec_srl_b16h, s390_vsrl, 0, BT_OV_BV8HI_BV8HI_UV8HI) +OB_DEF_VAR (s390_vec_srl_b16s, s390_vsrl, 0, BT_OV_BV8HI_BV8HI_UV4SI) +OB_DEF_VAR (s390_vec_srl_u32q, s390_vsrl, 0, BT_OV_UV4SI_UV4SI_UV16QI) +OB_DEF_VAR (s390_vec_srl_u32h, s390_vsrl, 0, BT_OV_UV4SI_UV4SI_UV8HI) +OB_DEF_VAR (s390_vec_srl_u32s, s390_vsrl, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_srl_s32q, s390_vsrl, 0, BT_OV_V4SI_V4SI_UV16QI) +OB_DEF_VAR (s390_vec_srl_s32h, s390_vsrl, 0, BT_OV_V4SI_V4SI_UV8HI) +OB_DEF_VAR (s390_vec_srl_s32s, s390_vsrl, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_srl_b32q, s390_vsrl, 0, BT_OV_BV4SI_BV4SI_UV16QI) +OB_DEF_VAR (s390_vec_srl_b32h, s390_vsrl, 0, BT_OV_BV4SI_BV4SI_UV8HI) +OB_DEF_VAR (s390_vec_srl_b32s, s390_vsrl, 0, BT_OV_BV4SI_BV4SI_UV4SI) +OB_DEF_VAR (s390_vec_srl_u64q, s390_vsrl, 0, BT_OV_UV2DI_UV2DI_UV16QI) +OB_DEF_VAR (s390_vec_srl_u64h, s390_vsrl, 0, BT_OV_UV2DI_UV2DI_UV8HI) +OB_DEF_VAR (s390_vec_srl_u64s, s390_vsrl, 0, BT_OV_UV2DI_UV2DI_UV4SI) +OB_DEF_VAR (s390_vec_srl_s64q, s390_vsrl, 0, BT_OV_V2DI_V2DI_UV16QI) +OB_DEF_VAR (s390_vec_srl_s64h, s390_vsrl, 0, BT_OV_V2DI_V2DI_UV8HI) +OB_DEF_VAR (s390_vec_srl_s64s, s390_vsrl, 0, BT_OV_V2DI_V2DI_UV4SI) +OB_DEF_VAR (s390_vec_srl_b64q, s390_vsrl, 0, BT_OV_BV2DI_BV2DI_UV16QI) +OB_DEF_VAR (s390_vec_srl_b64h, s390_vsrl, 0, BT_OV_BV2DI_BV2DI_UV8HI) +OB_DEF_VAR (s390_vec_srl_b64s, s390_vsrl, 0, BT_OV_BV2DI_BV2DI_UV4SI) + +B_DEF (s390_vsrl, vec_srlv16qiv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_srb, s390_vec_srb_u8_u8, s390_vec_srb_dbl_s64,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_srb_u8_u8, s390_vsrlb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_srb_u8_s8, s390_vsrlb, 0, BT_OV_UV16QI_UV16QI_V16QI) +OB_DEF_VAR (s390_vec_srb_s8_u8, s390_vsrlb, 0, BT_OV_V16QI_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_srb_s8_s8, s390_vsrlb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vec_srb_u16_u16, s390_vsrlb, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_srb_u16_s16, s390_vsrlb, 0, BT_OV_UV8HI_UV8HI_V8HI) +OB_DEF_VAR (s390_vec_srb_s16_u16, s390_vsrlb, 0, BT_OV_V8HI_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_srb_s16_s16, s390_vsrlb, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vec_srb_u32_u32, s390_vsrlb, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_srb_u32_s32, s390_vsrlb, 0, BT_OV_UV4SI_UV4SI_V4SI) +OB_DEF_VAR (s390_vec_srb_s32_u32, s390_vsrlb, 0, BT_OV_V4SI_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_srb_s32_s32, s390_vsrlb, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vec_srb_u64_u64, s390_vsrlb, 0, BT_OV_UV2DI_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_srb_u64_s64, s390_vsrlb, 0, BT_OV_UV2DI_UV2DI_V2DI) +OB_DEF_VAR (s390_vec_srb_s64_u64, s390_vsrlb, 0, BT_OV_V2DI_V2DI_UV2DI) +OB_DEF_VAR (s390_vec_srb_s64_s64, s390_vsrlb, 0, BT_OV_V2DI_V2DI_V2DI) +OB_DEF_VAR (s390_vec_srb_dbl_u64, s390_vsrlb, 0, BT_OV_V2DF_V2DF_UV2DI) +OB_DEF_VAR (s390_vec_srb_dbl_s64, s390_vsrlb, 0, BT_OV_V2DF_V2DF_V2DI) + +B_DEF (s390_vsrlb, vec_srbv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vsq, vec_sub_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_subc, s390_vec_subc_u8, s390_vec_subc_u64, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_subc_u8, s390_vscbib, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_subc_u16, s390_vscbih, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_subc_u32, s390_vscbif, 0, BT_OV_UV4SI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_subc_u64, s390_vscbig, 0, BT_OV_UV2DI_UV2DI_UV2DI) + +B_DEF (s390_vscbib, vec_subcv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vscbih, vec_subcv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vscbif, vec_subcv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vscbig, vec_subcv2di, 0, 0, BT_FN_UV2DI_UV2DI_UV2DI) +B_DEF (s390_vscbiq, vec_subc_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vsbiq, vec_sube_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vsbcbiq, vec_subec_u128, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI) + +OB_DEF (s390_vec_sum2, s390_vec_sum2_u16, s390_vec_sum2_u32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sum2_u16, s390_vsumgh, 0, BT_OV_UV2DI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_sum2_u32, s390_vsumgf, 0, BT_OV_UV2DI_UV4SI_UV4SI) + +B_DEF (s390_vsumgh, vec_sum2v8hi, 0, 0, BT_FN_UV2DI_UV8HI_UV8HI) +B_DEF (s390_vsumgf, vec_sum2v4si, 0, 0, BT_FN_UV2DI_UV4SI_UV4SI) + +OB_DEF (s390_vec_sum_u128, s390_vec_sum_u128_u32,s390_vec_sum_u128_u64,BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sum_u128_u32, s390_vsumqf, 0, BT_OV_UV16QI_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_sum_u128_u64, s390_vsumqg, 0, BT_OV_UV16QI_UV2DI_UV2DI) + +B_DEF (s390_vsumqf, vec_sum_u128v4si, 0, 0, BT_FN_UV16QI_UV4SI_UV4SI) +B_DEF (s390_vsumqg, vec_sum_u128v2di, 0, 0, BT_FN_UV16QI_UV2DI_UV2DI) + +OB_DEF (s390_vec_sum4, s390_vec_sum4_u8, s390_vec_sum4_u16, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_sum4_u8, s390_vsumb, 0, BT_OV_UV4SI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_sum4_u16, s390_vsumh, 0, BT_OV_UV4SI_UV8HI_UV8HI) + +B_DEF (s390_vsumb, vec_sum4v16qi, 0, 0, BT_FN_UV4SI_UV16QI_UV16QI) +B_DEF (s390_vsumh, vec_sum4v8hi, 0, 0, BT_FN_UV4SI_UV8HI_UV8HI) + +OB_DEF (s390_vec_test_mask, s390_vec_test_mask_s8,s390_vec_test_mask_dbl,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vec_test_mask_s8, s390_vtm, 0, BT_OV_INT_V16QI_UV16QI) +OB_DEF_VAR (s390_vec_test_mask_u8, s390_vtm, 0, BT_OV_INT_UV16QI_UV16QI) +OB_DEF_VAR (s390_vec_test_mask_s16, s390_vtm, 0, BT_OV_INT_V8HI_UV8HI) +OB_DEF_VAR (s390_vec_test_mask_u16, s390_vtm, 0, BT_OV_INT_UV8HI_UV8HI) +OB_DEF_VAR (s390_vec_test_mask_s32, s390_vtm, 0, BT_OV_INT_V4SI_UV4SI) +OB_DEF_VAR (s390_vec_test_mask_u32, s390_vtm, 0, BT_OV_INT_UV4SI_UV4SI) +OB_DEF_VAR (s390_vec_test_mask_s64, s390_vtm, 0, BT_OV_INT_V2DI_UV2DI) +OB_DEF_VAR (s390_vec_test_mask_u64, s390_vtm, 0, BT_OV_INT_UV2DI_UV2DI) +OB_DEF_VAR (s390_vec_test_mask_dbl, s390_vtm, 0, BT_OV_INT_V2DF_UV2DI) + +B_DEF (s390_vtm, vec_test_mask_intv16qi,0, 0, BT_FN_INT_UV16QI_UV16QI) +B_DEF (s390_vfaeb, vfaev16qi, 0, O3_U4, BT_FN_UV16QI_UV16QI_UV16QI_INT) +B_DEF (s390_vfaeh, vfaev8hi, 0, O3_U4, BT_FN_UV8HI_UV8HI_UV8HI_INT) +B_DEF (s390_vfaef, vfaev4si, 0, O3_U4, BT_FN_UV4SI_UV4SI_UV4SI_INT) +B_DEF (s390_vfaezb, vfaezv16qi, 0, O3_U4, BT_FN_UV16QI_UV16QI_UV16QI_INT) +B_DEF (s390_vfaezh, vfaezv8hi, 0, O3_U4, BT_FN_UV8HI_UV8HI_UV8HI_INT) +B_DEF (s390_vfaezf, vfaezv4si, 0, O3_U4, BT_FN_UV4SI_UV4SI_UV4SI_INT) +B_DEF (s390_vfaebs, vfaesv16qi, 0, O3_U4, BT_FN_UV16QI_UV16QI_UV16QI_INT_INTPTR) +B_DEF (s390_vfaehs, vfaesv8hi, 0, O3_U4, BT_FN_UV8HI_UV8HI_UV8HI_INT_INTPTR) +B_DEF (s390_vfaefs, vfaesv4si, 0, O3_U4, BT_FN_UV4SI_UV4SI_UV4SI_INT_INTPTR) +B_DEF (s390_vfaezbs, vfaezsv16qi, 0, O3_U4, BT_FN_UV16QI_UV16QI_UV16QI_INT_INTPTR) +B_DEF (s390_vfaezhs, vfaezsv8hi, 0, O3_U4, BT_FN_UV8HI_UV8HI_UV8HI_INT_INTPTR) +B_DEF (s390_vfaezfs, vfaezsv4si, 0, O3_U4, BT_FN_UV4SI_UV4SI_UV4SI_INT_INTPTR) + +OB_DEF (s390_vec_find_any_eq_idx, s390_vfaeb_idx_s8, s390_vfaef_idx_u32b,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaeb_idx_s8, s390_vfaeb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaeb_idx_u8a, s390_vfaeb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaeb_idx_u8b, s390_vfaeb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaeh_idx_s16, s390_vfaeh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaeh_idx_u16a, s390_vfaeh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaeh_idx_u16b, s390_vfaeh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaef_idx_s32, s390_vfaef, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaef_idx_u32a, s390_vfaef, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaef_idx_u32b, s390_vfaef, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_ne_idx, s390_vfaeb_inv_idx_s8,s390_vfaef_inv_idx_u32b,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaeb_inv_idx_s8, s390_vfaeb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaeb_inv_idx_u8a, s390_vfaeb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaeb_inv_idx_u8b, s390_vfaeb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaeh_inv_idx_s16, s390_vfaeh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaeh_inv_idx_u16a, s390_vfaeh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaeh_inv_idx_u16b, s390_vfaeh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaef_inv_idx_s32, s390_vfaef, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaef_inv_idx_u32a, s390_vfaef, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaef_inv_idx_u32b, s390_vfaef, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_eq_or_0_idx,s390_vfaezb_idx_s8,s390_vfaezf_idx_u32b,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaezb_idx_s8, s390_vfaezb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaezb_idx_u8a, s390_vfaezb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaezb_idx_u8b, s390_vfaezb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaezh_idx_s16, s390_vfaezh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaezh_idx_u16a, s390_vfaezh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaezh_idx_u16b, s390_vfaezh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaezf_idx_s32, s390_vfaezf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaezf_idx_u32a, s390_vfaezf, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaezf_idx_u32b, s390_vfaezf, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_ne_or_0_idx,s390_vfaezb_inv_idx_s8,s390_vfaezf_inv_idx_u32b,BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaezb_inv_idx_s8, s390_vfaezb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaezb_inv_idx_u8a, s390_vfaezb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaezb_inv_idx_u8b, s390_vfaezb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaezh_inv_idx_s16, s390_vfaezh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaezh_inv_idx_u16a, s390_vfaezh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaezh_inv_idx_u16b, s390_vfaezh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaezf_inv_idx_s32, s390_vfaezf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaezf_inv_idx_u32a, s390_vfaezf, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaezf_inv_idx_u32b, s390_vfaezf, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_eq, s390_vfaeb_s8, s390_vfaef_b32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaeb_s8, s390_vfaeb, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaeb_u8, s390_vfaeb, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaeb_b8, s390_vfaeb, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaeh_s16, s390_vfaeh, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaeh_u16, s390_vfaeh, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaeh_b16, s390_vfaeh, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaef_s32, s390_vfaef, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaef_u32, s390_vfaef, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaef_b32, s390_vfaef, 0, BT_OV_BV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_ne, s390_vfaeb_inv_s8, s390_vfaef_inv_b32, BT_FN_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfaeb_inv_s8, s390_vfaeb, 0, BT_OV_BV16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfaeb_inv_u8, s390_vfaeb, 0, BT_OV_BV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfaeb_inv_b8, s390_vfaeb, 0, BT_OV_BV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfaeh_inv_s16, s390_vfaeh, 0, BT_OV_BV8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfaeh_inv_u16, s390_vfaeh, 0, BT_OV_BV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfaeh_inv_b16, s390_vfaeh, 0, BT_OV_BV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfaef_inv_s32, s390_vfaef, 0, BT_OV_BV4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfaef_inv_u32, s390_vfaef, 0, BT_OV_BV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfaef_inv_b32, s390_vfaef, 0, BT_OV_BV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_find_any_eq_idx_cc,s390_vfaebs_idx_s8, s390_vfaefs_idx_u32b,BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaebs_idx_s8, s390_vfaebs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_idx_u8a, s390_vfaebs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_idx_u8b, s390_vfaebs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaehs_idx_s16, s390_vfaehs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_idx_u16a, s390_vfaehs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_idx_u16b, s390_vfaehs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaefs_idx_s32, s390_vfaefs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_idx_u32a, s390_vfaefs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_idx_u32b, s390_vfaefs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_find_any_ne_idx_cc,s390_vfaebs_inv_idx_s8,s390_vfaefs_inv_idx_u32b,BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_idx_s8, s390_vfaebs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_idx_u8a, s390_vfaebs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_idx_u8b, s390_vfaebs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_idx_s16, s390_vfaehs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_idx_u16a, s390_vfaehs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_idx_u16b, s390_vfaehs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_idx_s32, s390_vfaefs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_idx_u32a, s390_vfaefs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_idx_u32b, s390_vfaefs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_find_any_eq_or_0_idx_cc,s390_vfaezbs_idx_s8,s390_vfaezfs_idx_u32b,BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_idx_s8, s390_vfaezbs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_idx_u8a, s390_vfaezbs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_idx_u8b, s390_vfaezbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_idx_s16, s390_vfaezhs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_idx_u16a, s390_vfaezhs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_idx_u16b, s390_vfaezhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_idx_s32, s390_vfaezfs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_idx_u32a, s390_vfaezfs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_idx_u32b, s390_vfaezfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_find_any_ne_or_0_idx_cc,s390_vfaezbs_inv_idx_s8,s390_vfaezfs_inv_idx_u32b,BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_inv_idx_s8, s390_vfaezbs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_inv_idx_u8a, s390_vfaezbs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaezbs_inv_idx_u8b, s390_vfaezbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_inv_idx_s16, s390_vfaezhs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_inv_idx_u16a, s390_vfaezhs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaezhs_inv_idx_u16b, s390_vfaezhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_inv_idx_s32, s390_vfaezfs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_inv_idx_u32a, s390_vfaezfs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaezfs_inv_idx_u32b, s390_vfaezfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_find_any_eq_cc, s390_vfaebs_s8, s390_vfaefs_b32, BT_FN_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaebs_s8, s390_vfaebs, 0, BT_OV_BV16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_u8, s390_vfaebs, 0, BT_OV_BV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_b8, s390_vfaebs, 0, BT_OV_BV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaehs_s16, s390_vfaehs, 0, BT_OV_BV8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_u16, s390_vfaehs, 0, BT_OV_BV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_b16, s390_vfaehs, 0, BT_OV_BV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaefs_s32, s390_vfaefs, 0, BT_OV_BV4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_u32, s390_vfaefs, 0, BT_OV_BV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_b32, s390_vfaefs, 0, BT_OV_BV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_find_any_ne_cc, s390_vfaebs_inv_s8, s390_vfaefs_inv_b32,BT_FN_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_s8, s390_vfaebs, 0, BT_OV_BV16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_u8, s390_vfaebs, 0, BT_OV_BV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfaebs_inv_b8, s390_vfaebs, 0, BT_OV_BV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_s16, s390_vfaehs, 0, BT_OV_BV8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_u16, s390_vfaehs, 0, BT_OV_BV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfaehs_inv_b16, s390_vfaehs, 0, BT_OV_BV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_s32, s390_vfaefs, 0, BT_OV_BV4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_u32, s390_vfaefs, 0, BT_OV_BV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfaefs_inv_b32, s390_vfaefs, 0, BT_OV_BV4SI_UV4SI_UV4SI_INTPTR) + +B_DEF (s390_vfeeb, vfeev16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vfeeh, vfeev8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vfeef, vfeev4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vfeezb, vfeezv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vfeezh, vfeezv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vfeezf, vfeezv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vfeebs, vfeesv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vfeehs, vfeesv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vfeefs, vfeesv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_INTPTR) +B_DEF (s390_vfeezbs, vfeezsv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vfeezhs, vfeezsv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vfeezfs, vfeezsv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpeq_idx, s390_vfeeb_s8, s390_vfeef_u32b, BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfeeb_s8, s390_vfeeb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfeeb_u8a, s390_vfeeb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfeeb_u8b, s390_vfeeb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfeeh_s16, s390_vfeeh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfeeh_u16a, s390_vfeeh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfeeh_u16b, s390_vfeeh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfeef_s32, s390_vfeef, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfeef_u32a, s390_vfeef, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfeef_u32b, s390_vfeef, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpeq_or_0_idx, s390_vfeezb_s8, s390_vfeezf_u32b, BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfeezb_s8, s390_vfeezb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfeezb_u8a, s390_vfeezb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfeezb_u8b, s390_vfeezb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfeezh_s16, s390_vfeezh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfeezh_u16a, s390_vfeezh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfeezh_u16b, s390_vfeezh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfeezf_s32, s390_vfeezf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfeezf_u32a, s390_vfeezf, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfeezf_u32b, s390_vfeezf, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpeq_idx_cc, s390_vfeebs_s8, s390_vfeefs_u32b, BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfeebs_s8, s390_vfeebs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfeebs_u8a, s390_vfeebs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfeebs_u8b, s390_vfeebs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfeehs_s16, s390_vfeehs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfeehs_u16a, s390_vfeehs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfeehs_u16b, s390_vfeehs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfeefs_s32, s390_vfeefs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfeefs_u32a, s390_vfeefs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfeefs_u32b, s390_vfeefs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpeq_or_0_idx_cc, s390_vfeezbs_s8, s390_vfeezfs_u32b, BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfeezbs_s8, s390_vfeezbs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfeezbs_u8a, s390_vfeezbs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfeezbs_u8b, s390_vfeezbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfeezhs_s16, s390_vfeezhs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfeezhs_u16a, s390_vfeezhs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfeezhs_u16b, s390_vfeezhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfeezfs_s32, s390_vfeezfs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfeezfs_u32a, s390_vfeezfs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfeezfs_u32b, s390_vfeezfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +B_DEF (s390_vfeneb, vfenev16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vfeneh, vfenev8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vfenef, vfenev4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vfenezb, vfenezv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI) +B_DEF (s390_vfenezh, vfenezv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI) +B_DEF (s390_vfenezf, vfenezv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI) +B_DEF (s390_vfenebs, vfenesv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vfenehs, vfenesv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vfenefs, vfenesv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_INTPTR) +B_DEF (s390_vfenezbs, vfenezsv16qi, 0, 0, BT_FN_UV16QI_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vfenezhs, vfenezsv8hi, 0, 0, BT_FN_UV8HI_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vfenezfs, vfenezsv4si, 0, 0, BT_FN_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpne_idx, s390_vfeneb_s8, s390_vfenef_u32b, BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfeneb_s8, s390_vfeneb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfeneb_u8a, s390_vfeneb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfeneb_u8b, s390_vfeneb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfeneh_s16, s390_vfeneh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfeneh_u16a, s390_vfeneh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfeneh_u16b, s390_vfeneh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfenef_s32, s390_vfenef, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfenef_u32a, s390_vfenef, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfenef_u32b, s390_vfenef, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpne_or_0_idx, s390_vfenezb_s8, s390_vfenezf_u32b, BT_FN_INT_OV4SI_OV4SI) +OB_DEF_VAR (s390_vfenezb_s8, s390_vfenezb, 0, BT_OV_V16QI_V16QI_V16QI) +OB_DEF_VAR (s390_vfenezb_u8a, s390_vfenezb, 0, BT_OV_UV16QI_BV16QI_BV16QI) +OB_DEF_VAR (s390_vfenezb_u8b, s390_vfenezb, 0, BT_OV_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vfenezh_s16, s390_vfenezh, 0, BT_OV_V8HI_V8HI_V8HI) +OB_DEF_VAR (s390_vfenezh_u16a, s390_vfenezh, 0, BT_OV_UV8HI_BV8HI_BV8HI) +OB_DEF_VAR (s390_vfenezh_u16b, s390_vfenezh, 0, BT_OV_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vfenezf_s32, s390_vfenezf, 0, BT_OV_V4SI_V4SI_V4SI) +OB_DEF_VAR (s390_vfenezf_u32a, s390_vfenezf, 0, BT_OV_UV4SI_BV4SI_BV4SI) +OB_DEF_VAR (s390_vfenezf_u32b, s390_vfenezf, 0, BT_OV_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpne_idx_cc, s390_vfenebs_s8, s390_vfenefs_u32b, BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfenebs_s8, s390_vfenebs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfenebs_u8a, s390_vfenebs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfenebs_u8b, s390_vfenebs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfenehs_s16, s390_vfenehs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfenehs_u16a, s390_vfenehs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfenehs_u16b, s390_vfenehs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfenefs_s32, s390_vfenefs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfenefs_u32a, s390_vfenefs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfenefs_u32b, s390_vfenefs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpne_or_0_idx_cc, s390_vfenezbs_s8, s390_vfenezfs_u32b, BT_FN_INT_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vfenezbs_s8, s390_vfenezbs, 0, BT_OV_V16QI_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vfenezbs_u8a, s390_vfenezbs, 0, BT_OV_UV16QI_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vfenezbs_u8b, s390_vfenezbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vfenezhs_s16, s390_vfenezhs, 0, BT_OV_V8HI_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vfenezhs_u16a, s390_vfenezhs, 0, BT_OV_UV8HI_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vfenezhs_u16b, s390_vfenezhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vfenezfs_s32, s390_vfenezfs, 0, BT_OV_V4SI_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vfenezfs_u32a, s390_vfenezfs, 0, BT_OV_UV4SI_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vfenezfs_u32b, s390_vfenezfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_INTPTR) + +B_DEF (s390_vistrb, vistrv16qi, 0, 0, BT_FN_UV16QI_UV16QI) +B_DEF (s390_vistrh, vistrv8hi, 0, 0, BT_FN_UV8HI_UV8HI) +B_DEF (s390_vistrf, vistrv4si, 0, 0, BT_FN_UV4SI_UV4SI) +B_DEF (s390_vistrbs, vistrsv16qi, 0, 0, BT_FN_UV16QI_UV16QI_INTPTR) +B_DEF (s390_vistrhs, vistrsv8hi, 0, 0, BT_FN_UV8HI_UV8HI_INTPTR) +B_DEF (s390_vistrfs, vistrsv4si, 0, 0, BT_FN_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cp_until_zero, s390_vistrb_s8, s390_vistrf_u32, BT_FN_OV4SI_OV4SI) +OB_DEF_VAR (s390_vistrb_s8, s390_vistrb, 0, BT_OV_V16QI_V16QI) +OB_DEF_VAR (s390_vistrb_b8, s390_vistrb, 0, BT_OV_BV16QI_BV16QI) +OB_DEF_VAR (s390_vistrb_u8, s390_vistrb, 0, BT_OV_UV16QI_UV16QI) +OB_DEF_VAR (s390_vistrh_s16, s390_vistrh, 0, BT_OV_V8HI_V8HI) +OB_DEF_VAR (s390_vistrh_b16, s390_vistrh, 0, BT_OV_BV8HI_BV8HI) +OB_DEF_VAR (s390_vistrh_u16, s390_vistrh, 0, BT_OV_UV8HI_UV8HI) +OB_DEF_VAR (s390_vistrf_s32, s390_vistrf, 0, BT_OV_V4SI_V4SI) +OB_DEF_VAR (s390_vistrf_b32, s390_vistrf, 0, BT_OV_BV4SI_BV4SI) +OB_DEF_VAR (s390_vistrf_u32, s390_vistrf, 0, BT_OV_UV4SI_UV4SI) + +OB_DEF (s390_vec_cp_until_zero_cc, s390_vistrbs_s8, s390_vistrfs_u32, BT_FN_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vistrbs_s8, s390_vistrbs, 0, BT_OV_V16QI_V16QI_INTPTR) +OB_DEF_VAR (s390_vistrbs_b8, s390_vistrbs, 0, BT_OV_BV16QI_BV16QI_INTPTR) +OB_DEF_VAR (s390_vistrbs_u8, s390_vistrbs, 0, BT_OV_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vistrhs_s16, s390_vistrhs, 0, BT_OV_V8HI_V8HI_INTPTR) +OB_DEF_VAR (s390_vistrhs_b16, s390_vistrhs, 0, BT_OV_BV8HI_BV8HI_INTPTR) +OB_DEF_VAR (s390_vistrhs_u16, s390_vistrhs, 0, BT_OV_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vistrfs_s32, s390_vistrfs, 0, BT_OV_V4SI_V4SI_INTPTR) +OB_DEF_VAR (s390_vistrfs_b32, s390_vistrfs, 0, BT_OV_BV4SI_BV4SI_INTPTR) +OB_DEF_VAR (s390_vistrfs_u32, s390_vistrfs, 0, BT_OV_UV4SI_UV4SI_INTPTR) + +B_DEF (s390_vstrcb, vstrcv16qi, 0, O4_U4, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT) +B_DEF (s390_vstrch, vstrcv8hi, 0, O4_U4, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT) +B_DEF (s390_vstrcf, vstrcv4si, 0, O4_U4, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT) +B_DEF (s390_vstrczb, vstrczv16qi, 0, O4_U4, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT) +B_DEF (s390_vstrczh, vstrczv8hi, 0, O4_U4, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT) +B_DEF (s390_vstrczf, vstrczv4si, 0, O4_U4, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT) +B_DEF (s390_vstrcbs, vstrcsv16qi, 0, O4_U4, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT_INTPTR) +B_DEF (s390_vstrchs, vstrcsv8hi, 0, O4_U4, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT_INTPTR) +B_DEF (s390_vstrcfs, vstrcsv4si, 0, O4_U4, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT_INTPTR) +B_DEF (s390_vstrczbs, vstrczsv16qi, 0, O4_U4, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT_INTPTR) +B_DEF (s390_vstrczhs, vstrczsv8hi, 0, O4_U4, BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT_INTPTR) +B_DEF (s390_vstrczfs, vstrczsv4si, 0, O4_U4, BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT_INTPTR) + +OB_DEF (s390_vec_cmprg_idx, s390_vstrcb_idx_u8, s390_vstrcf_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrcb_idx_u8, s390_vstrcb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrch_idx_u16, s390_vstrch, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrcf_idx_u32, s390_vstrcf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpnrg_idx, s390_vstrcb_inv_idx_u8,s390_vstrcf_inv_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrcb_inv_idx_u8, s390_vstrcb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrch_inv_idx_u16, s390_vstrch, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrcf_inv_idx_u32, s390_vstrcf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmprg_or_0_idx, s390_vstrczb_idx_u8,s390_vstrczf_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrczb_idx_u8, s390_vstrczb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrczh_idx_u16, s390_vstrczh, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrczf_idx_u32, s390_vstrczf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpnrg_or_0_idx, s390_vstrczb_inv_idx_u8,s390_vstrczf_inv_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrczb_inv_idx_u8, s390_vstrczb, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrczh_inv_idx_u16, s390_vstrczh, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrczf_inv_idx_u32, s390_vstrczf, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmprg, s390_vstrcb_u8, s390_vstrcf_u32, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrcb_u8, s390_vstrcb, 0, BT_OV_BV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrch_u16, s390_vstrch, 0, BT_OV_BV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrcf_u32, s390_vstrcf, 0, BT_OV_BV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmpnrg, s390_vstrcb_inv_u8, s390_vstrcf_inv_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) +OB_DEF_VAR (s390_vstrcb_inv_u8, s390_vstrcb, 0, BT_OV_BV16QI_UV16QI_UV16QI_UV16QI) +OB_DEF_VAR (s390_vstrch_inv_u16, s390_vstrch, 0, BT_OV_BV8HI_UV8HI_UV8HI_UV8HI) +OB_DEF_VAR (s390_vstrcf_inv_u32, s390_vstrcf, 0, BT_OV_BV4SI_UV4SI_UV4SI_UV4SI) + +OB_DEF (s390_vec_cmprg_idx_cc, s390_vstrcbs_idx_u8,s390_vstrcfs_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrcbs_idx_u8, s390_vstrcbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vstrchs_idx_u16, s390_vstrchs, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vstrcfs_idx_u32, s390_vstrcfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpnrg_idx_cc, s390_vstrcbs_inv_idx_u8,s390_vstrcfs_inv_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrcbs_inv_idx_u8, s390_vstrcbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR) /* vstrcb */ +OB_DEF_VAR (s390_vstrchs_inv_idx_u16, s390_vstrchs, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI_INTPTR) /* vstrch */ +OB_DEF_VAR (s390_vstrcfs_inv_idx_u32, s390_vstrcfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI_INTPTR) /* vstrcf */ + +OB_DEF (s390_vec_cmprg_or_0_idx_cc, s390_vstrczbs_idx_u8,s390_vstrczfs_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrczbs_idx_u8, s390_vstrczbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vstrczhs_idx_u16, s390_vstrczhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vstrczfs_idx_u32, s390_vstrczfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpnrg_or_0_idx_cc,s390_vstrczbs_inv_idx_u8,s390_vstrczfs_inv_idx_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrczbs_inv_idx_u8, s390_vstrczbs, 0, BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vstrczhs_inv_idx_u16, s390_vstrczhs, 0, BT_OV_UV8HI_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vstrczfs_inv_idx_u32, s390_vstrczfs, 0, BT_OV_UV4SI_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmprg_cc, s390_vstrcbs_u8, s390_vstrcfs_u32, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrcbs_u8, s390_vstrcbs, 0, BT_OV_BV16QI_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vstrchs_u16, s390_vstrchs, 0, BT_OV_BV8HI_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vstrcfs_u32, s390_vstrcfs, 0, BT_OV_BV4SI_UV4SI_UV4SI_UV4SI_INTPTR) + +OB_DEF (s390_vec_cmpnrg_cc, s390_vstrcbs_inv_u8,s390_vstrcfs_inv_u32,BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR) +OB_DEF_VAR (s390_vstrcbs_inv_u8, s390_vstrcbs, 0, BT_OV_BV16QI_UV16QI_UV16QI_UV16QI_INTPTR) +OB_DEF_VAR (s390_vstrchs_inv_u16, s390_vstrchs, 0, BT_OV_BV8HI_UV8HI_UV8HI_UV8HI_INTPTR) +OB_DEF_VAR (s390_vstrcfs_inv_u32, s390_vstrcfs, 0, BT_OV_BV4SI_UV4SI_UV4SI_UV4SI_INTPTR) + +B_DEF (s390_vec_all_nge, vec_all_unltv2df, 0, 0, BT_FN_INT_V2DF_V2DF) +B_DEF (s390_vec_all_ngt, vec_all_unlev2df, 0, 0, BT_FN_INT_V2DF_V2DF) +B_DEF (s390_vec_any_nge, vec_any_unltv2df, 0, 0, BT_FN_INT_V2DF_V2DF) +B_DEF (s390_vec_any_ngt, vec_any_unlev2df, 0, 0, BT_FN_INT_V2DF_V2DF) + +OB_DEF (s390_vec_ctd, s390_vec_ctd_s64, s390_vec_ctd_u64, BT_FN_V2DF_UV4SI_INT) +OB_DEF_VAR (s390_vec_ctd_s64, s390_vec_ctd_s64, O2_U5, BT_OV_V2DF_V2DI_INT) /* vcdgb */ +OB_DEF_VAR (s390_vec_ctd_u64, s390_vec_ctd_u64, O2_U5, BT_OV_V2DF_UV2DI_INT) /* vcdlgb */ + +B_DEF (s390_vec_ctd_s64, vec_ctd_s64, 0, O2_U5, BT_FN_V2DF_V2DI_INT) /* vcdgb */ +B_DEF (s390_vec_ctd_u64, vec_ctd_u64, 0, O2_U5, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */ +B_DEF (s390_vcdgb, vec_di_to_df_s64, 0, O2_U5, BT_FN_V2DF_V2DI_INT) +B_DEF (s390_vcdlgb, vec_di_to_df_u64, 0, O2_U5, BT_FN_V2DF_UV2DI_INT) +B_DEF (s390_vec_ctsl, vec_ctsl, 0, O2_U5, BT_FN_V2DI_V2DF_INT) /* vcgdb */ +B_DEF (s390_vec_ctul, vec_ctul, 0, O2_U5, BT_FN_UV2DI_V2DF_INT) /* vclgdb */ +B_DEF (s390_vcgdb, vec_df_to_di_s64, 0, O2_U5, BT_FN_V2DI_V2DF_INT) +B_DEF (s390_vclgdb, vec_df_to_di_u64, 0, O2_U5, BT_FN_UV2DI_V2DF_INT) +B_DEF (s390_vfidb, vfidb, 0, O2_U4 | O3_U4, BT_FN_V2DF_V2DF_UCHAR_UCHAR) +B_DEF (s390_vec_ld2f, vec_ld2f, 0, 0, BT_FN_V2DF_FLTCONSTPTR) /* vldeb */ +B_DEF (s390_vec_st2f, vec_st2f, 0, 0, BT_FN_VOID_V2DF_FLTPTR) /* vledb */ +B_DEF (s390_vfmadb, fmav2df4, 0, 0, BT_FN_V2DF_V2DF_V2DF_V2DF) +B_DEF (s390_vfmsdb, fmsv2df4, 0, 0, BT_FN_V2DF_V2DF_V2DF_V2DF) +B_DEF (s390_vflndb, vec_nabs, 0, 0, BT_FN_V2DF_V2DF) +B_DEF (s390_vfsqdb, sqrtv2df2, 0, 0, BT_FN_V2DF_V2DF) +B_DEF (s390_vftcidb, vftcidb, 0, O2_U12, BT_FN_V2DI_V2DF_INT_INTPTR) diff --git a/gcc/config/s390/s390-builtins.h b/gcc/config/s390/s390-builtins.h new file mode 100644 index 00000000000..043c098efa1 --- /dev/null +++ b/gcc/config/s390/s390-builtins.h @@ -0,0 +1,160 @@ +/* Common data structures used for builtin handling on S/390. + Copyright (C) 2015 Free Software Foundation, Inc. + + Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +/* This files contains data structure definitions which can be used by + s390-builtins.c as well as s390-c.c. Since the latter is + considered to be part of the front-end we have to be careful not + to use any of tree and rtx like data structures. */ + +/* Builtin types, data and prototypes. */ + +enum s390_builtin_type_index +{ +#undef DEF_TYPE +#undef DEF_POINTER_TYPE +#undef DEF_DISTINCT_TYPE +#undef DEF_VECTOR_TYPE +#undef DEF_OPAQUE_VECTOR_TYPE +#undef DEF_FN_TYPE +#undef DEF_OV_TYPE +#define DEF_TYPE(INDEX, NODE, CONST_P) INDEX, +#define DEF_POINTER_TYPE(INDEX, INDEX2) INDEX, +#define DEF_DISTINCT_TYPE(INDEX, INDEX2) INDEX, +#define DEF_VECTOR_TYPE(INDEX, INDEX2, ELEMENTS) INDEX, +#define DEF_OPAQUE_VECTOR_TYPE(INDEX, INDEX2, ELEMENTS) INDEX, +#define DEF_FN_TYPE(...) +#define DEF_OV_TYPE(...) +#include "s390-builtin-types.def" + BT_MAX +}; + +enum s390_builtin_fn_type_index +{ +#undef DEF_TYPE +#undef DEF_POINTER_TYPE +#undef DEF_DISTINCT_TYPE +#undef DEF_VECTOR_TYPE +#undef DEF_OPAQUE_VECTOR_TYPE +#undef DEF_FN_TYPE +#undef DEF_OV_TYPE +#define DEF_TYPE(...) +#define DEF_POINTER_TYPE(...) +#define DEF_DISTINCT_TYPE(...) +#define DEF_VECTOR_TYPE(...) +#define DEF_OPAQUE_VECTOR_TYPE(...) +#define DEF_FN_TYPE(INDEX, ...) INDEX, +#define DEF_OV_TYPE(...) +#include "s390-builtin-types.def" + BT_FN_MAX +}; + +enum s390_builtin_ov_type_index +{ +#undef DEF_TYPE +#undef DEF_POINTER_TYPE +#undef DEF_DISTINCT_TYPE +#undef DEF_VECTOR_TYPE +#undef DEF_OPAQUE_VECTOR_TYPE +#undef DEF_FN_TYPE +#undef DEF_OV_TYPE +#define DEF_TYPE(...) +#define DEF_POINTER_TYPE(...) +#define DEF_DISTINCT_TYPE(...) +#define DEF_VECTOR_TYPE(...) +#define DEF_OPAQUE_VECTOR_TYPE(...) +#define DEF_FN_TYPE(...) +#define DEF_OV_TYPE(INDEX, ...) INDEX, +#include "s390-builtin-types.def" + BT_OV_MAX +}; + +#define MAX_OV_OPERANDS 6 + +extern tree s390_builtin_types[BT_MAX]; +extern tree s390_builtin_fn_types[BT_FN_MAX]; + + /* Builtins. */ + +enum s390_builtins { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(NAME, ...) S390_BUILTIN_##NAME, +#define OB_DEF(...) +#define OB_DEF_VAR(...) + +#include "s390-builtins.def" + S390_BUILTIN_MAX +}; + + +/* Generate an enumeration of all overloaded builtins defined with + OB_DEF in s390-builtins.def. */ +enum s390_overloaded_builtins { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(NAME, ...) S390_OVERLOADED_BUILTIN_##NAME, +#define OB_DEF_VAR(...) +#include "s390-builtins.def" +S390_OVERLOADED_BUILTIN_MAX +}; + +/* Generate an enumeration of all variants of overloaded builtins + defined with OB_DEF_VAR in s390-builtins.def. */ +enum s390_overloaded_builtin_vars { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(...) +#define OB_DEF_VAR(NAME, ...) S390_OVERLOADED_BUILTIN_VAR_##NAME, +#include "s390-builtins.def" +S390_OVERLOADED_BUILTIN_VAR_MAX +}; + +#define S390_OVERLOADED_BUILTIN_OFFSET S390_BUILTIN_MAX +#define S390_OVERLOADED_BUILTIN_VAR_OFFSET \ + (S390_BUILTIN_MAX + S390_OVERLOADED_BUILTIN_MAX) +#define S390_ALL_BUILTIN_MAX \ + (S390_BUILTIN_MAX + S390_OVERLOADED_BUILTIN_MAX + \ + S390_OVERLOADED_BUILTIN_VAR_MAX) + +extern const unsigned int flags_builtin[S390_BUILTIN_MAX + 1]; +extern const unsigned int + flags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1]; + +static inline unsigned int +flags_for_builtin (int fcode) +{ + if (fcode >= S390_OVERLOADED_BUILTIN_VAR_OFFSET) + return flags_overloaded_builtin_var[fcode - + S390_OVERLOADED_BUILTIN_VAR_OFFSET]; + else if (fcode >= S390_OVERLOADED_BUILTIN_OFFSET) + gcc_unreachable (); + else + return flags_builtin[fcode]; +} + +extern tree s390_builtin_decls[S390_BUILTIN_MAX + + S390_OVERLOADED_BUILTIN_MAX + + S390_OVERLOADED_BUILTIN_VAR_MAX]; diff --git a/gcc/config/s390/s390-c.c b/gcc/config/s390/s390-c.c new file mode 100644 index 00000000000..ed81b0f86b4 --- /dev/null +++ b/gcc/config/s390/s390-c.c @@ -0,0 +1,907 @@ +/* Language specific subroutines used for code generation on IBM S/390 + and zSeries + Copyright (C) 2015 Free Software Foundation, Inc. + + Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . + + Based on gcc/config/rs6000/rs6000-c.c. + + In GCC terms this file belongs to the frontend. It will be + compiled with -DIN_GCC_FRONTEND. With that rtl.h cannot be + included anymore - a mechanism supposed to avoid adding frontend - + backend dependencies. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "cpplib.h" +#include "hash-set.h" +#include "machmode.h" +#include "vec.h" +#include "double-int.h" +#include "input.h" +#include "alias.h" +#include "symtab.h" +#include "wide-int.h" +#include "inchash.h" +#include "tree.h" +#include "fold-const.h" +#include "stringpool.h" +#include "c-family/c-common.h" +#include "c-family/c-pragma.h" +#include "diagnostic-core.h" +#include "tm_p.h" +#include "target.h" +#include "langhooks.h" +#include "tree-pretty-print.h" +#include "c/c-tree.h" + +#include "s390-builtins.h" + +static GTY(()) tree __vector_keyword; +static GTY(()) tree vector_keyword; +static GTY(()) tree __bool_keyword; +static GTY(()) tree bool_keyword; +static GTY(()) tree _Bool_keyword; + + +/* Generate an array holding all the descriptions of variants of + overloaded builtins defined with OB_DEF_VAR in + s390-builtins.def. */ +static enum s390_builtin_ov_type_index +type_for_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] = + { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(...) +#define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FNTYPE, +#include "s390-builtins.def" + BT_OV_MAX + }; + + +/* Generate an array indexed by an overloaded builtin index returning + the first index in desc_for_overloaded_builtin_var where the + variants for the builtin can be found. */ +static enum s390_overloaded_builtin_vars +desc_start_for_overloaded_builtin[S390_OVERLOADED_BUILTIN_MAX + 1] = + { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, FNTYPE) \ + S390_OVERLOADED_BUILTIN_VAR_##FIRST_VAR_NAME, +#define OB_DEF_VAR(...) + #include "s390-builtins.def" + S390_OVERLOADED_BUILTIN_VAR_MAX + }; + +/* Generate an array indexed by an overloaded builtin index returning + the last index in desc_for_overloaded_builtin_var where the + variants for the builtin can be found. */ +static enum s390_overloaded_builtin_vars +desc_end_for_overloaded_builtin[S390_OVERLOADED_BUILTIN_MAX + 1] = + { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, FNTYPE) \ + S390_OVERLOADED_BUILTIN_VAR_##LAST_VAR_NAME, +#define OB_DEF_VAR(...) + #include "s390-builtins.def" + S390_OVERLOADED_BUILTIN_VAR_MAX + }; + +static enum s390_builtin_type_index +s390_builtin_ov_types[BT_OV_MAX][MAX_OV_OPERANDS] = + { +#undef DEF_TYPE +#undef DEF_POINTER_TYPE +#undef DEF_DISTINCT_TYPE +#undef DEF_VECTOR_TYPE +#undef DEF_OPAQUE_VECTOR_TYPE +#undef DEF_FN_TYPE +#undef DEF_OV_TYPE +#define DEF_TYPE(...) +#define DEF_POINTER_TYPE(...) +#define DEF_DISTINCT_TYPE(...) +#define DEF_VECTOR_TYPE(...) +#define DEF_OPAQUE_VECTOR_TYPE(...) +#define DEF_FN_TYPE(...) +#define DEF_OV_TYPE(INDEX, args...) { args }, +#include "s390-builtin-types.def" + }; + +static const enum s390_builtins bt_for_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX] = { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(...) +#define OB_DEF_VAR(NAME, BT, ...) S390_BUILTIN_##BT, + +#include "s390-builtins.def" + }; + +/* In addition to calling fold_convert for EXPR of type TYPE, also + call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be + hiding there (PR47197). */ +tree +fully_fold_convert (tree type, tree expr) +{ + tree result = fold_convert (type, expr); + bool maybe_const = true; + + if (!c_dialect_cxx ()) + result = c_fully_fold (result, false, &maybe_const); + + return result; +} + +/* Unify the different variants to the same nodes in order to keep the + code working with it simple. */ +static cpp_hashnode * +s390_categorize_keyword (const cpp_token *tok) +{ + if (tok->type == CPP_NAME) + { + cpp_hashnode *ident = tok->val.node.node; + + if (ident == C_CPP_HASHNODE (vector_keyword)) + return C_CPP_HASHNODE (__vector_keyword); + + if (ident == C_CPP_HASHNODE (bool_keyword)) + return C_CPP_HASHNODE (__bool_keyword); + + if (ident == C_CPP_HASHNODE (_Bool_keyword)) + return C_CPP_HASHNODE (__bool_keyword); + return ident; + } + + return 0; +} + + +/* Called to decide whether a conditional macro should be expanded. + Since we have exactly one such macro (i.e, 'vector'), we do not + need to examine the 'tok' parameter. */ + +static cpp_hashnode * +s390_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) +{ + cpp_hashnode *expand_this = tok->val.node.node; + cpp_hashnode *ident; + static bool expand_bool_p = false; + int idx = 0; + enum rid rid_code; + + /* The vector keyword is only expanded if the machine actually + provides hardware support. */ + if (!TARGET_ZVECTOR) + return NULL; + + ident = s390_categorize_keyword (tok); + + /* Triggered when we picked a different variant in + s390_categorize_keyword. */ + if (ident != expand_this) + expand_this = NULL; + + /* The vector keyword has been found already and we remembered to + expand the next bool. */ + if (expand_bool_p && ident == C_CPP_HASHNODE (__bool_keyword)) + { + expand_bool_p = false; + return ident; + } + + if (ident != C_CPP_HASHNODE (__vector_keyword)) + return expand_this; + + do + tok = cpp_peek_token (pfile, idx++); + while (tok->type == CPP_PADDING); + ident = s390_categorize_keyword (tok); + + if (!ident) + return expand_this; + + /* vector bool - remember to expand the next bool. */ + if (ident == C_CPP_HASHNODE (__bool_keyword)) + { + expand_bool_p = true; + return C_CPP_HASHNODE (__vector_keyword); + } + + /* The boost libraries have code with Iterator::vector vector in it. + If we allow the normal handling, this module will be called + recursively, and the vector will be skipped.; */ + if (ident == C_CPP_HASHNODE (__vector_keyword)) + return expand_this; + + rid_code = (enum rid)(ident->rid_code); + + if (ident->type == NT_MACRO) + { + /* Now actually fetch the tokens we "peeked" before and do a + lookahead for the next. */ + do + (void) cpp_get_token (pfile); + while (--idx > 0); + do + tok = cpp_peek_token (pfile, idx++); + while (tok->type == CPP_PADDING); + ident = s390_categorize_keyword (tok); + + if (ident == C_CPP_HASHNODE (__bool_keyword)) + { + expand_bool_p = true; + return C_CPP_HASHNODE (__vector_keyword); + } + else if (ident) + rid_code = (enum rid)(ident->rid_code); + } + + /* vector keyword followed by type identifier: vector unsigned, + vector long, ... + Types consisting of more than one identifier are not supported by + zvector e.g. long long, long double, unsigned long int. */ + if (rid_code == RID_UNSIGNED || rid_code == RID_LONG + || rid_code == RID_SHORT || rid_code == RID_SIGNED + || rid_code == RID_INT || rid_code == RID_CHAR + || rid_code == RID_DOUBLE) + { + expand_this = C_CPP_HASHNODE (__vector_keyword); + /* If the next keyword is bool, it will need to be expanded as + well. */ + do + tok = cpp_peek_token (pfile, idx++); + while (tok->type == CPP_PADDING); + ident = s390_categorize_keyword (tok); + + /* __vector long __bool a; */ + if (ident == C_CPP_HASHNODE (__bool_keyword)) + expand_bool_p = true; + else + { + /* Triggered with: __vector long long __bool a; */ + do + tok = cpp_peek_token (pfile, idx++); + while (tok->type == CPP_PADDING); + ident = s390_categorize_keyword (tok); + + if (ident == C_CPP_HASHNODE (__bool_keyword)) + expand_bool_p = true; + } + } + + return expand_this; +} + +/* Define platform dependent macros. */ +void +s390_cpu_cpp_builtins (cpp_reader *pfile) +{ + cpp_assert (pfile, "cpu=s390"); + cpp_assert (pfile, "machine=s390"); + cpp_define (pfile, "__s390__"); + if (TARGET_ZARCH) + cpp_define (pfile, "__zarch__"); + if (TARGET_64BIT) + cpp_define (pfile, "__s390x__"); + if (TARGET_LONG_DOUBLE_128) + cpp_define (pfile, "__LONG_DOUBLE_128__"); + if (TARGET_HTM) + cpp_define (pfile, "__HTM__"); + if (TARGET_ZVECTOR) + { + cpp_define (pfile, "__VEC__=10301"); + cpp_define (pfile, "__vector=__attribute__((vector_size(16)))"); + cpp_define (pfile, "__bool=__attribute__((s390_vector_bool)) unsigned"); + + if (!flag_iso) + { + cpp_define (pfile, "__VECTOR_KEYWORD_SUPPORTED__"); + cpp_define (pfile, "vector=vector"); + cpp_define (pfile, "bool=bool"); + + __vector_keyword = get_identifier ("__vector"); + C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; + + vector_keyword = get_identifier ("vector"); + C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL; + + __bool_keyword = get_identifier ("__bool"); + C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL; + + bool_keyword = get_identifier ("bool"); + C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL; + + _Bool_keyword = get_identifier ("_Bool"); + C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; + + /* Enable context-sensitive macros. */ + cpp_get_callbacks (pfile)->macro_to_expand = s390_macro_to_expand; + } + } +} + +/* Expand builtins which can directly be mapped to tree expressions. + LOC - location information + FCODE - function code of the builtin + ARGLIST - value supposed to be passed as arguments + RETURN-TYPE - expected return type of the builtin */ +static tree +s390_expand_overloaded_builtin (location_t loc, + unsigned fcode, + vec *arglist, + tree return_type) +{ + switch (fcode) + { + case S390_OVERLOADED_BUILTIN_s390_vec_step: + if (TREE_CODE (TREE_TYPE ((*arglist)[0])) != VECTOR_TYPE) + { + error_at (loc, "Builtin vec_step can only be used on vector types."); + return error_mark_node; + } + return build_int_cst (NULL_TREE, + TYPE_VECTOR_SUBPARTS (TREE_TYPE ((*arglist)[0]))); + case S390_OVERLOADED_BUILTIN_s390_vec_xld2: + case S390_OVERLOADED_BUILTIN_s390_vec_xlw4: + return build2 (MEM_REF, return_type, + fold_build_pointer_plus ((*arglist)[1], (*arglist)[0]), + build_int_cst (TREE_TYPE ((*arglist)[1]), 0)); + case S390_OVERLOADED_BUILTIN_s390_vec_xstd2: + case S390_OVERLOADED_BUILTIN_s390_vec_xstw4: + return build2 (MODIFY_EXPR, TREE_TYPE((*arglist)[0]), + build1 (INDIRECT_REF, TREE_TYPE((*arglist)[0]), + fold_build_pointer_plus ((*arglist)[2], (*arglist)[1])), + (*arglist)[0]); + case S390_OVERLOADED_BUILTIN_s390_vec_load_pair: + return build_constructor_va (return_type, 2, + NULL_TREE, (*arglist)[0], + NULL_TREE, (*arglist)[1]); + default: + gcc_unreachable (); + } +} + +/* invert result */ +#define __VSTRING_FLAG_IN 8 +/* result type */ +#define __VSTRING_FLAG_RT 4 +/* zero search */ +#define __VSTRING_FLAG_ZS 2 +/* set condition code */ +#define __VSTRING_FLAG_CS 1 + +/* Return the flags value to be used for string low-level builtins + when expanded from overloaded builtin OB_FCODE. */ +static unsigned int +s390_get_vstring_flags (int ob_fcode) +{ + unsigned int flags = 0; + + switch (ob_fcode) + { + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_cc: + flags |= __VSTRING_FLAG_IN; + break; + default: + break; + } + switch (ob_fcode) + { + + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx_cc: + flags |= __VSTRING_FLAG_RT; + break; + default: + break; + } + switch (ob_fcode) + { + + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx_cc: + flags |= __VSTRING_FLAG_ZS; + break; + default: + break; + } + switch (ob_fcode) + { + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_cc: + flags |= __VSTRING_FLAG_CS; + break; + default: + break; + } + return flags; +} +#undef __VSTRING_FLAG_IN +#undef __VSTRING_FLAG_RT +#undef __VSTRING_FLAG_ZS +#undef __VSTRING_FLAG_CS + +/* For several overloaded builtins the argument lists do not match + exactly the signature of a low-level builtin. This function + adjusts the argument list ARGLIST for the overloaded builtin + OB_FCODE to the signature of the low-level builtin given by + DECL. */ +static void +s390_adjust_builtin_arglist (unsigned int ob_fcode, tree decl, + vec **arglist) +{ + tree arg_chain; + int src_arg_index, dest_arg_index; + vec *folded_args = NULL; + + /* We at most add one more operand to the list. */ + vec_alloc (folded_args, (*arglist)->allocated () + 1); + for (arg_chain = TYPE_ARG_TYPES (TREE_TYPE (decl)), + src_arg_index = 0, dest_arg_index = 0; + !VOID_TYPE_P (TREE_VALUE (arg_chain)); + arg_chain = TREE_CHAIN (arg_chain), dest_arg_index++) + { + bool arg_assigned_p = false; + switch (ob_fcode) + { + /* For all these the low level builtin needs an additional flags parameter. */ + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_eq_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_find_any_ne_cc: + if (dest_arg_index == 2) + { + folded_args->quick_push (build_int_cst (integer_type_node, + s390_get_vstring_flags (ob_fcode))); + arg_assigned_p = true; + } + break; + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_or_0_idx_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmprg_cc: + case S390_OVERLOADED_BUILTIN_s390_vec_cmpnrg_cc: + if (dest_arg_index == 3) + { + folded_args->quick_push (build_int_cst (integer_type_node, + s390_get_vstring_flags (ob_fcode))); + arg_assigned_p = true; + } + break; + case S390_OVERLOADED_BUILTIN_s390_vec_sel: + case S390_OVERLOADED_BUILTIN_s390_vec_insert: + case S390_OVERLOADED_BUILTIN_s390_vec_load_len: + /* Swap the first to arguments. It is better to do it here + instead of the header file to avoid operand checking + throwing error messages for a weird operand index. */ + if (dest_arg_index < 2) + { + folded_args->quick_push (fully_fold_convert (TREE_VALUE (arg_chain), + (**arglist)[1 - dest_arg_index])); + src_arg_index++; + arg_assigned_p = true; + } + break; + case S390_OVERLOADED_BUILTIN_s390_vec_store_len: + if (dest_arg_index == 1 || dest_arg_index == 2) + { + folded_args->quick_push (fully_fold_convert (TREE_VALUE (arg_chain), + (**arglist)[3 - dest_arg_index])); + src_arg_index++; + arg_assigned_p = true; + } + break; + + case S390_OVERLOADED_BUILTIN_s390_vec_load_bndry: + { + int code; + + if (dest_arg_index == 1) + { + switch (tree_to_uhwi ((**arglist)[src_arg_index])) + { + case 64: code = 0; break; + case 128: code = 1; break; + case 256: code = 2; break; + case 512: code = 3; break; + case 1024: code = 4; break; + case 2048: code = 5; break; + case 4096: code = 6; break; + default: + error ("valid values for builtin %qF argument %d are 64, " + "128, 256, 512, 1024, 2048, and 4096", decl, + src_arg_index + 1); + return; + } + folded_args->quick_push (build_int_cst (integer_type_node, + code)); + src_arg_index++; + arg_assigned_p = true; + } + } + break; + case S390_OVERLOADED_BUILTIN_s390_vec_rl_mask: + /* Duplicate the first src arg. */ + if (dest_arg_index == 0) + { + folded_args->quick_push (fully_fold_convert (TREE_VALUE (arg_chain), + (**arglist)[src_arg_index])); + arg_assigned_p = true; + } + break; + default: + break; + } + if (!arg_assigned_p) + { + folded_args->quick_push (fully_fold_convert (TREE_VALUE (arg_chain), + (**arglist)[src_arg_index])); + src_arg_index++; + } + } + *arglist = folded_args; +} + +/* Check whether the arguments in ARGLIST match the function type + DEF_TYPE. Return the number of argument types which required + conversion/promotion in order to make it match. + 0 stands for a perfect match - all operand types match without changes + INT_MAX stands for a mismatch. */ +static int +s390_fn_types_compatible (enum s390_builtin_ov_type_index typeindex, + vec *arglist) +{ + unsigned int i; + int match_type = 0; + + for (i = 0; i < vec_safe_length (arglist); i++) + { + tree b_arg_type = s390_builtin_types[s390_builtin_ov_types[typeindex][i + 1]]; + tree in_arg = (*arglist)[i]; + tree in_type = TREE_TYPE (in_arg); + + if (TREE_CODE (b_arg_type) == VECTOR_TYPE) + { + /* Vector types have to match precisely. */ + if (b_arg_type != in_type + && TYPE_MAIN_VARIANT (b_arg_type) != TYPE_MAIN_VARIANT (in_type)) + goto mismatch; + } + + if (lang_hooks.types_compatible_p (in_type, b_arg_type)) + continue; + + if (lang_hooks.types_compatible_p ( + lang_hooks.types.type_promotes_to (in_type), + lang_hooks.types.type_promotes_to (b_arg_type))) + { + match_type++; + continue; + } + + /* In this stage the C++ frontend would go ahead trying to find + implicit conversion chains for the argument to match the + target type. We will mimic this here only for our limited + subset of argument types. */ + if (TREE_CODE (b_arg_type) == INTEGER_TYPE + && TREE_CODE (in_type) == INTEGER_TYPE) + { + match_type++; + continue; + } + + /* If the incoming pointer argument has more qualifiers than the + argument type it can still be an imperfect match. */ + if (POINTER_TYPE_P (b_arg_type) && POINTER_TYPE_P (in_type) + && !(TYPE_QUALS (TREE_TYPE (in_type)) + & ~TYPE_QUALS (TREE_TYPE (b_arg_type))) + && (TYPE_QUALS (TREE_TYPE (b_arg_type)) + & ~TYPE_QUALS (TREE_TYPE (in_type)))) + { + tree qual_in_type = + build_qualified_type (TREE_TYPE (in_type), + TYPE_QUALS (TREE_TYPE (b_arg_type))); + + if (lang_hooks.types_compatible_p (qual_in_type, + TREE_TYPE (b_arg_type))) + { + match_type++; + continue; + } + } + + mismatch: + if (TARGET_DEBUG_ARG) + fprintf (stderr, " mismatch in operand: %d\n", i + 1); + return INT_MAX; + } + + return match_type; +} + +/* Return the number of elements in the vector arguments of FNDECL in + case all it matches for all vector arguments, -1 otherwise. */ +static int +s390_vec_n_elem (tree fndecl) +{ + tree b_arg_chain; + int n_elem = -1; + + if (TREE_CODE (TREE_TYPE (TREE_TYPE (fndecl))) == VECTOR_TYPE) + n_elem = TYPE_VECTOR_SUBPARTS (TREE_TYPE (TREE_TYPE ((fndecl)))); + + for (b_arg_chain = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); + !VOID_TYPE_P (TREE_VALUE (b_arg_chain)); + b_arg_chain = TREE_CHAIN (b_arg_chain)) + { + int tmp_n_elem; + if (TREE_CODE (TREE_VALUE (b_arg_chain)) != VECTOR_TYPE) + continue; + tmp_n_elem = TYPE_VECTOR_SUBPARTS (TREE_VALUE (b_arg_chain)); + if (n_elem != -1 && n_elem != tmp_n_elem) + return -1; + n_elem = tmp_n_elem; + } + return n_elem; +} + + +/* Return a tree expression for a call to the overloaded builtin + function OB_FNDECL at LOC with arguments PASSED_ARGLIST. */ +tree +s390_resolve_overloaded_builtin (location_t loc, + tree ob_fndecl, + void *passed_arglist) +{ + vec *arglist = static_cast *> (passed_arglist); + unsigned int in_args_num = vec_safe_length (arglist); + unsigned int ob_args_num = 0; + unsigned int ob_fcode = DECL_FUNCTION_CODE (ob_fndecl); + enum s390_overloaded_builtin_vars bindex; + unsigned int i; + int last_match_type = INT_MAX; + int last_match_index = -1; + unsigned int all_op_flags; + int num_matches = 0; + tree target_builtin_decl, b_arg_chain, return_type; + enum s390_builtin_ov_type_index last_match_fntype_index; + + if (TARGET_DEBUG_ARG) + fprintf (stderr, + "s390_resolve_overloaded_builtin, code = %4d, %s - %s overloaded\n", + (int)ob_fcode, IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)), + ob_fcode < S390_BUILTIN_MAX ? "not" : ""); + + /* 0...S390_BUILTIN_MAX-1 is for non-overloaded builtins. */ + if (ob_fcode < S390_BUILTIN_MAX) + { + if (flags_for_builtin(ob_fcode) & B_INT) + { + error_at (loc, + "Builtin %qF is for GCC internal use only.", + ob_fndecl); + return error_mark_node; + } + return NULL_TREE; + } + + ob_fcode -= S390_BUILTIN_MAX; + + for (b_arg_chain = TYPE_ARG_TYPES (TREE_TYPE (ob_fndecl)); + !VOID_TYPE_P (TREE_VALUE (b_arg_chain)); + b_arg_chain = TREE_CHAIN (b_arg_chain)) + ob_args_num++; + + if (ob_args_num != in_args_num) + { + error_at (loc, + "Mismatch in number of arguments for builtin %qF. " + "Expected: %d got %d", ob_fndecl, + ob_args_num, in_args_num); + return error_mark_node; + } + + for (i = 0; i < in_args_num; i++) + if ((*arglist)[i] == error_mark_node) + return error_mark_node; + + /* Overloaded builtins without any variants are directly expanded here. */ + if (desc_start_for_overloaded_builtin[ob_fcode] == + S390_OVERLOADED_BUILTIN_VAR_MAX) + return s390_expand_overloaded_builtin (loc, ob_fcode, arglist, NULL_TREE); + + for (bindex = desc_start_for_overloaded_builtin[ob_fcode]; + bindex <= desc_end_for_overloaded_builtin[ob_fcode]; + bindex = (enum s390_overloaded_builtin_vars)((int)bindex + 1)) + { + int match_type; + enum s390_builtin_ov_type_index type_index = + type_for_overloaded_builtin_var[bindex]; + + if (TARGET_DEBUG_ARG) + fprintf (stderr, "checking variant number: %d", (int)bindex); + + match_type = s390_fn_types_compatible (type_index, arglist); + + if (match_type == INT_MAX) + continue; + + if (TARGET_DEBUG_ARG) + fprintf (stderr, + " %s match score: %d\n", match_type == 0 ? "perfect" : "imperfect", + match_type); + + if (match_type < last_match_type) + { + num_matches = 1; + last_match_type = match_type; + last_match_fntype_index = type_index; + last_match_index = bindex; + } + else if (match_type == last_match_type) + num_matches++; + } + + if (last_match_type == INT_MAX) + { + error_at (loc, "invalid parameter combination for intrinsic"); + return error_mark_node; + } + else if (num_matches > 1) + { + error_at (loc, "ambiguous overload for intrinsic: %s\n", + IDENTIFIER_POINTER (DECL_NAME (ob_fndecl))); + return error_mark_node; + } + + if (bt_for_overloaded_builtin_var[last_match_index] == S390_BUILTIN_MAX) + target_builtin_decl = ob_fndecl; + else + target_builtin_decl = s390_builtin_decls[bt_for_overloaded_builtin_var[last_match_index]]; + + all_op_flags = flags_overloaded_builtin_var[last_match_index]; + return_type = s390_builtin_types[s390_builtin_ov_types[last_match_fntype_index][0]]; + + /* Check for the operand flags in the overloaded builtin variant. */ + for (i = 0; i < ob_args_num; i++) + { + unsigned int op_flags = all_op_flags & ((1 << O_SHIFT) - 1); + tree arg = (*arglist)[i]; + tree type = s390_builtin_types[s390_builtin_ov_types[last_match_fntype_index][i + 1]]; + + all_op_flags = all_op_flags >> O_SHIFT; + + if (op_flags == O_ELEM) + { + int n_elem = s390_vec_n_elem (target_builtin_decl); + gcc_assert (n_elem > 0); + gcc_assert (type == integer_type_node); + (*arglist)[i] = build2 (BIT_AND_EXPR, integer_type_node, + fold_convert (integer_type_node, arg), + build_int_cst (NULL_TREE, n_elem - 1)); + } + + if (TREE_CODE (arg) != INTEGER_CST || !O_IMM_P (op_flags)) + continue; + + if ((TYPE_UNSIGNED (type) + && !int_fits_type_p (arg, c_common_unsigned_type (type))) + || (!TYPE_UNSIGNED (type) + && !int_fits_type_p (arg, c_common_signed_type (type)))) + { + error("constant argument %d for builtin %qF is out " + "of range for target type", + i + 1, target_builtin_decl); + return error_mark_node; + } + + if (TREE_CODE (arg) == INTEGER_CST + && !s390_const_operand_ok (arg, i + 1, op_flags, target_builtin_decl)) + return error_mark_node; + } + + /* Handle builtins we expand directly - without mapping it to a low + level builtin. */ + if (bt_for_overloaded_builtin_var[last_match_index] == S390_BUILTIN_MAX) + return s390_expand_overloaded_builtin (loc, ob_fcode, arglist, return_type); + + s390_adjust_builtin_arglist (ob_fcode, target_builtin_decl, &arglist); + + if (VOID_TYPE_P (return_type)) + return build_function_call_vec (loc, vNULL, target_builtin_decl, + arglist, NULL); + else + return fully_fold_convert (return_type, + build_function_call_vec (loc, vNULL, target_builtin_decl, + arglist, NULL)); +} + +/* This is used to define the REGISTER_TARGET_PRAGMAS macro in s390.h. */ +void +s390_register_target_pragmas (void) +{ + targetm.resolve_overloaded_builtin = s390_resolve_overloaded_builtin; +} diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def index 26c0a8165a2..f4c53f82552 100644 --- a/gcc/config/s390/s390-modes.def +++ b/gcc/config/s390/s390-modes.def @@ -87,9 +87,21 @@ CCA -> CCAP, CCAN Vector comparison modes CCVEQ EQ - - NE (VCEQ) +CCVEQANY EQ EQ - NE (VCEQ) + +CCVH GT - - LE (VCH) +CCVHANY GT GT - LE (VCH) +CCVHU GTU - - LEU (VCHL) +CCVHUANY GTU GTU - LEU (VCHL) CCVFH GT - - UNLE (VFCH) +CCVFHANY GT GT - UNLE (VFCH) CCVFHE GE - - UNLT (VFCHE) +CCVFHEANY GE GE - UNLT (VFCHE) + + + + *** Comments *** CCAP, CCAN @@ -157,6 +169,15 @@ The compare and swap instructions sets the condition code to 0/1 if the operands were equal/unequal. The CCZ1 mode ensures the result can be effectively placed into a register. + +CCV* + +The variants with and without ANY are generated by the same +instructions and therefore are holding the same information. However, +when generating a condition code mask they require checking different +bits of CC. In that case the variants without ANY represent the +results for *all* elements. + CCRAW The cc mode generated by a non-compare instruction. The condition @@ -188,8 +209,17 @@ CC_MODE (CCT3); CC_MODE (CCRAW); CC_MODE (CCVEQ); +CC_MODE (CCVEQANY); + +CC_MODE (CCVH); +CC_MODE (CCVHANY); +CC_MODE (CCVHU); +CC_MODE (CCVHUANY); + CC_MODE (CCVFH); +CC_MODE (CCVFHANY); CC_MODE (CCVFHE); +CC_MODE (CCVFHEANY); /* Vector modes. */ diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h index b23806f8669..a8b885476dd 100644 --- a/gcc/config/s390/s390-protos.h +++ b/gcc/config/s390/s390-protos.h @@ -97,6 +97,7 @@ extern void s390_expand_atomic (machine_mode, enum rtx_code, rtx, rtx, rtx, bool); extern void s390_expand_tbegin (rtx, rtx, rtx, bool); extern void s390_expand_vec_compare (rtx, enum rtx_code, rtx, rtx); +extern void s390_expand_vec_compare_cc (rtx, enum rtx_code, rtx, rtx, bool); extern void s390_expand_vcond (rtx, rtx, rtx, enum rtx_code, rtx, rtx); extern void s390_expand_vec_init (rtx, rtx); extern rtx s390_return_addr_rtx (int, rtx); @@ -124,3 +125,10 @@ extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT); extern void s390_asm_output_function_label (FILE *, const char *, tree); #endif /* RTX_CODE */ + +/* s390-c.c routines */ +extern void s390_cpu_cpp_builtins (struct cpp_reader *); +extern void s390_register_target_pragmas (void); + +/* Routines for s390-c.c */ +extern bool s390_const_operand_ok (tree, int, int, tree); diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 68a92a92946..7fd59699410 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -465,6 +465,398 @@ struct GTY(()) machine_function bytes on a z10 (or higher) CPU. */ #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) + +/* System z builtins. */ + +#include "s390-builtins.h" + +const unsigned int flags_builtin[S390_BUILTIN_MAX + 1] = + { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(NAME, PATTERN, ATTRS, FLAGS, FNTYPE) FLAGS, +#define OB_DEF(...) +#define OB_DEF_VAR(...) +#include "s390-builtins.def" + 0 + }; + +const unsigned int flags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] = + { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(...) +#define OB_DEF(...) +#define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FLAGS, +#include "s390-builtins.def" + 0 + }; + +tree s390_builtin_types[BT_MAX]; +tree s390_builtin_fn_types[BT_FN_MAX]; +tree s390_builtin_decls[S390_BUILTIN_MAX + + S390_OVERLOADED_BUILTIN_MAX + + S390_OVERLOADED_BUILTIN_VAR_MAX]; + +static enum insn_code const code_for_builtin[S390_BUILTIN_MAX + 1] = { +#undef B_DEF +#undef OB_DEF +#undef OB_DEF_VAR +#define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN, +#define OB_DEF(...) +#define OB_DEF_VAR(...) + +#include "s390-builtins.def" + CODE_FOR_nothing +}; + +static void +s390_init_builtins (void) +{ + /* These definitions are being used in s390-builtins.def. */ + tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), + NULL, NULL); + tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); + tree c_uint64_type_node; + + /* The uint64_type_node from tree.c is not compatible to the C99 + uint64_t data type. What we want is c_uint64_type_node from + c-common.c. But since backend code is not supposed to interface + with the frontend we recreate it here. */ + if (TARGET_64BIT) + c_uint64_type_node = long_unsigned_type_node; + else + c_uint64_type_node = long_long_unsigned_type_node; + +#undef DEF_TYPE +#define DEF_TYPE(INDEX, NODE, CONST_P) \ + s390_builtin_types[INDEX] = (!CONST_P) ? \ + (NODE) : build_type_variant ((NODE), 1, 0); + +#undef DEF_POINTER_TYPE +#define DEF_POINTER_TYPE(INDEX, INDEX_BASE) \ + s390_builtin_types[INDEX] = \ + build_pointer_type (s390_builtin_types[INDEX_BASE]); + +#undef DEF_DISTINCT_TYPE +#define DEF_DISTINCT_TYPE(INDEX, INDEX_BASE) \ + s390_builtin_types[INDEX] = \ + build_distinct_type_copy (s390_builtin_types[INDEX_BASE]); + +#undef DEF_VECTOR_TYPE +#define DEF_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \ + s390_builtin_types[INDEX] = \ + build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS); + +#undef DEF_OPAQUE_VECTOR_TYPE +#define DEF_OPAQUE_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \ + s390_builtin_types[INDEX] = \ + build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS); + +#undef DEF_FN_TYPE +#define DEF_FN_TYPE(INDEX, args...) \ + s390_builtin_fn_types[INDEX] = \ + build_function_type_list (args, NULL_TREE); +#undef DEF_OV_TYPE +#define DEF_OV_TYPE(...) +#include "s390-builtin-types.def" + +#undef B_DEF +#define B_DEF(NAME, PATTERN, ATTRS, FLAGS, FNTYPE) \ + s390_builtin_decls[S390_BUILTIN_##NAME] = \ + add_builtin_function ("__builtin_" #NAME, \ + s390_builtin_fn_types[FNTYPE], \ + S390_BUILTIN_##NAME, \ + BUILT_IN_MD, \ + NULL, \ + ATTRS); +#undef OB_DEF +#define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, FNTYPE) \ + s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \ + add_builtin_function ("__builtin_" #NAME, \ + s390_builtin_fn_types[FNTYPE], \ + S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \ + BUILT_IN_MD, \ + NULL, \ + 0); +#undef OB_DEF_VAR +#define OB_DEF_VAR(...) +#include "s390-builtins.def" + +} + +/* Return true if ARG is appropriate as argument number ARGNUM of + builtin DECL. The operand flags from s390-builtins.def have to + passed as OP_FLAGS. */ +bool +s390_const_operand_ok (tree arg, int argnum, int op_flags, tree decl) +{ + if (O_UIMM_P (op_flags)) + { + int bitwidths[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 }; + int bitwidth = bitwidths[op_flags - O_U1]; + + if (!tree_fits_uhwi_p (arg) + || tree_to_uhwi (arg) > ((unsigned HOST_WIDE_INT)1 << bitwidth) - 1) + { + error("constant argument %d for builtin %qF is out of range (0.." + HOST_WIDE_INT_PRINT_UNSIGNED ")", + argnum, decl, + ((unsigned HOST_WIDE_INT)1 << bitwidth) - 1); + return false; + } + } + + if (O_SIMM_P (op_flags)) + { + int bitwidths[] = { 2, 3, 4, 5, 8, 12, 16, 32 }; + int bitwidth = bitwidths[op_flags - O_S2]; + + if (!tree_fits_shwi_p (arg) + || tree_to_shwi (arg) < -((HOST_WIDE_INT)1 << (bitwidth - 1)) + || tree_to_shwi (arg) > (((HOST_WIDE_INT)1 << (bitwidth - 1)) - 1)) + { + error("constant argument %d for builtin %qF is out of range (" + HOST_WIDE_INT_PRINT_DEC ".." + HOST_WIDE_INT_PRINT_DEC ")", + argnum, decl, + -(HOST_WIDE_INT)1 << (bitwidth - 1), + ((HOST_WIDE_INT)1 << (bitwidth - 1)) - 1); + return false; + } + } + return true; +} + +/* Expand an expression EXP that calls a built-in function, + with result going to TARGET if that's convenient + (and in mode MODE if that's convenient). + SUBTARGET may be used as the target for computing one of EXP's operands. + IGNORE is nonzero if the value is to be ignored. */ + +static rtx +s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, + machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) +{ +#define MAX_ARGS 5 + + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum insn_code icode; + rtx op[MAX_ARGS], pat; + int arity; + bool nonvoid; + tree arg; + call_expr_arg_iterator iter; + unsigned int all_op_flags = flags_for_builtin (fcode); + machine_mode last_vec_mode = VOIDmode; + + if (TARGET_DEBUG_ARG) + { + fprintf (stderr, + "s390_expand_builtin, code = %4d, %s\n", + (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); + } + + + if (fcode >= S390_OVERLOADED_BUILTIN_VAR_OFFSET + && fcode < S390_ALL_BUILTIN_MAX) + { + gcc_unreachable (); + } + else if (fcode < S390_OVERLOADED_BUILTIN_OFFSET) + { + icode = code_for_builtin[fcode]; + /* Set a flag in the machine specific cfun part in order to support + saving/restoring of FPRs. */ + if (fcode == S390_BUILTIN_tbegin || fcode == S390_BUILTIN_tbegin_retry) + cfun->machine->tbegin_p = true; + } + else if (fcode < S390_OVERLOADED_BUILTIN_VAR_OFFSET) + { + error ("Unresolved overloaded builtin"); + return const0_rtx; + } + else + internal_error ("bad builtin fcode"); + + if (icode == 0) + internal_error ("bad builtin icode"); + + nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; + + if (nonvoid) + { + machine_mode tmode = insn_data[icode].operand[0].mode; + if (!target + || GET_MODE (target) != tmode + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + + /* There are builtins (e.g. vec_promote) with no vector + arguments but an element selector. So we have to also look + at the vector return type when emitting the modulo + operation. */ + if (VECTOR_MODE_P (insn_data[icode].operand[0].mode)) + last_vec_mode = insn_data[icode].operand[0].mode; + } + + arity = 0; + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) + { + const struct insn_operand_data *insn_op; + unsigned int op_flags = all_op_flags & ((1 << O_SHIFT) - 1); + + all_op_flags = all_op_flags >> O_SHIFT; + + if (arg == error_mark_node) + return NULL_RTX; + if (arity >= MAX_ARGS) + return NULL_RTX; + + if (O_IMM_P (op_flags) + && TREE_CODE (arg) != INTEGER_CST) + { + error ("constant value required for builtin %qF argument %d", + fndecl, arity + 1); + return const0_rtx; + } + + if (!s390_const_operand_ok (arg, arity + 1, op_flags, fndecl)) + return const0_rtx; + + insn_op = &insn_data[icode].operand[arity + nonvoid]; + op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); + + /* Wrap the expanded RTX for pointer types into a MEM expr with + the proper mode. This allows us to use e.g. (match_operand + "memory_operand"..) in the insn patterns instead of (mem + (match_operand "address_operand)). This is helpful for + patterns not just accepting MEMs. */ + if (POINTER_TYPE_P (TREE_TYPE (arg)) + && insn_op->predicate != address_operand) + op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]); + + /* Expand the module operation required on element selectors. */ + if (op_flags == O_ELEM) + { + gcc_assert (last_vec_mode != VOIDmode); + op[arity] = simplify_expand_binop (SImode, code_to_optab (AND), + op[arity], + GEN_INT (GET_MODE_NUNITS (last_vec_mode) - 1), + NULL_RTX, 1, OPTAB_DIRECT); + } + + /* Record the vector mode used for an element selector. This assumes: + 1. There is no builtin with two different vector modes and an element selector + 2. The element selector comes after the vector type it is referring to. + This currently the true for all the builtins but FIXME we + should better check for that. */ + if (VECTOR_MODE_P (insn_op->mode)) + last_vec_mode = insn_op->mode; + + if (insn_op->predicate (op[arity], insn_op->mode)) + { + arity++; + continue; + } + + if (MEM_P (op[arity]) + && insn_op->predicate == memory_operand + && (GET_MODE (XEXP (op[arity], 0)) == Pmode + || GET_MODE (XEXP (op[arity], 0)) == VOIDmode)) + { + op[arity] = replace_equiv_address (op[arity], + copy_to_mode_reg (Pmode, + XEXP (op[arity], 0))); + } + else if (GET_MODE (op[arity]) == insn_op->mode + || GET_MODE (op[arity]) == VOIDmode + || (insn_op->predicate == address_operand + && GET_MODE (op[arity]) == Pmode)) + { + /* An address_operand usually has VOIDmode in the expander + so we cannot use this. */ + machine_mode target_mode = + (insn_op->predicate == address_operand + ? Pmode : insn_op->mode); + op[arity] = copy_to_mode_reg (target_mode, op[arity]); + } + + if (!insn_op->predicate (op[arity], insn_op->mode)) + { + error ("Invalid argument %d for builtin %qF", arity + 1, fndecl); + return const0_rtx; + } + arity++; + } + + if (last_vec_mode != VOIDmode && !TARGET_VX) + { + error ("Vector type builtin %qF is not supported without -mvx " + "(default with -march=z13).", + fndecl); + return const0_rtx; + } + + switch (arity) + { + case 0: + pat = GEN_FCN (icode) (target); + break; + case 1: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0]); + else + pat = GEN_FCN (icode) (op[0]); + break; + case 2: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0], op[1]); + else + pat = GEN_FCN (icode) (op[0], op[1]); + break; + case 3: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); + else + pat = GEN_FCN (icode) (op[0], op[1], op[2]); + break; + case 4: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); + else + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); + break; + case 5: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); + else + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); + break; + case 6: + if (nonvoid) + pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4], op[5]); + else + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); + break; + default: + gcc_unreachable (); + } + if (!pat) + return NULL_RTX; + emit_insn (pat); + + if (nonvoid) + return target; + else + return const0_rtx; +} + + static const int s390_hotpatch_hw_max = 1000000; static int s390_hotpatch_hw_before_label = 0; static int s390_hotpatch_hw_after_label = 0; @@ -514,9 +906,43 @@ s390_handle_hotpatch_attribute (tree *node, tree name, tree args, return NULL_TREE; } +/* Expand the s390_vector_bool type attribute. */ + +static tree +s390_handle_vectorbool_attribute (tree *node, tree name ATTRIBUTE_UNUSED, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) +{ + tree type = *node, result = NULL_TREE; + machine_mode mode; + + while (POINTER_TYPE_P (type) + || TREE_CODE (type) == FUNCTION_TYPE + || TREE_CODE (type) == METHOD_TYPE + || TREE_CODE (type) == ARRAY_TYPE) + type = TREE_TYPE (type); + + mode = TYPE_MODE (type); + switch (mode) + { + case DImode: case V2DImode: result = s390_builtin_types[BT_BV2DI]; break; + case SImode: case V4SImode: result = s390_builtin_types[BT_BV4SI]; break; + case HImode: case V8HImode: result = s390_builtin_types[BT_BV8HI]; break; + case QImode: case V16QImode: result = s390_builtin_types[BT_BV16QI]; + default: break; + } + + *no_add_attrs = true; /* No need to hang on to the attribute. */ + + if (result) + *node = lang_hooks.types.reconstruct_complex_type (*node, result); + + return NULL_TREE; +} + static const struct attribute_spec s390_attribute_table[] = { - { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute, false - }, + { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute, false }, + { "s390_vector_bool", 0, 0, false, true, false, s390_handle_vectorbool_attribute, true }, /* End element. */ { NULL, 0, 0, false, false, false, NULL, false } }; @@ -682,6 +1108,8 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode) case CCT2mode: case CCT3mode: case CCVEQmode: + case CCVHmode: + case CCVHUmode: case CCVFHmode: case CCVFHEmode: if (req_mode != set_mode) @@ -1416,6 +1844,49 @@ s390_branch_condition_mask (rtx code) case NE: return CC3; default: return -1; } + + case CCVEQANYmode: + switch (GET_CODE (code)) + { + case EQ: return CC0 | CC1; + case NE: return CC3 | CC1; + default: return -1; + } + + /* Integer vector compare modes. */ + + case CCVHmode: + switch (GET_CODE (code)) + { + case GT: return CC0; + case LE: return CC3; + default: return -1; + } + + case CCVHANYmode: + switch (GET_CODE (code)) + { + case GT: return CC0 | CC1; + case LE: return CC3 | CC1; + default: return -1; + } + + case CCVHUmode: + switch (GET_CODE (code)) + { + case GTU: return CC0; + case LEU: return CC3; + default: return -1; + } + + case CCVHUANYmode: + switch (GET_CODE (code)) + { + case GTU: return CC0 | CC1; + case LEU: return CC3 | CC1; + default: return -1; + } + /* FP vector compare modes. */ case CCVFHmode: @@ -1425,6 +1896,15 @@ s390_branch_condition_mask (rtx code) case UNLE: return CC3; default: return -1; } + + case CCVFHANYmode: + switch (GET_CODE (code)) + { + case GT: return CC0 | CC1; + case UNLE: return CC3 | CC1; + default: return -1; + } + case CCVFHEmode: switch (GET_CODE (code)) { @@ -1432,6 +1912,16 @@ s390_branch_condition_mask (rtx code) case UNLT: return CC3; default: return -1; } + + case CCVFHEANYmode: + switch (GET_CODE (code)) + { + case GE: return CC0 | CC1; + case UNLT: return CC3 | CC1; + default: return -1; + } + + case CCRAWmode: switch (GET_CODE (code)) { @@ -5359,6 +5849,93 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond, emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mode, target))); } +/* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into + TARGET if either all (ALL_P is true) or any (ALL_P is false) of the + elements in CMP1 and CMP2 fulfill the comparison. */ +void +s390_expand_vec_compare_cc (rtx target, enum rtx_code code, + rtx cmp1, rtx cmp2, bool all_p) +{ + enum rtx_code new_code = code; + machine_mode cmp_mode, full_cmp_mode, scratch_mode; + rtx tmp_reg = gen_reg_rtx (SImode); + bool swap_p = false; + + if (GET_MODE_CLASS (GET_MODE (cmp1)) == MODE_VECTOR_INT) + { + switch (code) + { + case EQ: cmp_mode = CCVEQmode; break; + case NE: cmp_mode = CCVEQmode; break; + case GT: cmp_mode = CCVHmode; break; + case GE: cmp_mode = CCVHmode; new_code = LE; swap_p = true; break; + case LT: cmp_mode = CCVHmode; new_code = GT; swap_p = true; break; + case LE: cmp_mode = CCVHmode; new_code = LE; break; + case GTU: cmp_mode = CCVHUmode; break; + case GEU: cmp_mode = CCVHUmode; new_code = LEU; swap_p = true; break; + case LTU: cmp_mode = CCVHUmode; new_code = GTU; swap_p = true; break; + case LEU: cmp_mode = CCVHUmode; new_code = LEU; break; + default: gcc_unreachable (); + } + scratch_mode = GET_MODE (cmp1); + } + else if (GET_MODE (cmp1) == V2DFmode) + { + switch (code) + { + case EQ: cmp_mode = CCVEQmode; break; + case NE: cmp_mode = CCVEQmode; break; + case GT: cmp_mode = CCVFHmode; break; + case GE: cmp_mode = CCVFHEmode; break; + case UNLE: cmp_mode = CCVFHmode; break; + case UNLT: cmp_mode = CCVFHEmode; break; + case LT: cmp_mode = CCVFHmode; new_code = GT; swap_p = true; break; + case LE: cmp_mode = CCVFHEmode; new_code = GE; swap_p = true; break; + default: gcc_unreachable (); + } + scratch_mode = V2DImode; + } + else + gcc_unreachable (); + + if (!all_p) + switch (cmp_mode) + { + case CCVEQmode: full_cmp_mode = CCVEQANYmode; break; + case CCVHmode: full_cmp_mode = CCVHANYmode; break; + case CCVHUmode: full_cmp_mode = CCVHUANYmode; break; + case CCVFHmode: full_cmp_mode = CCVFHANYmode; break; + case CCVFHEmode: full_cmp_mode = CCVFHEANYmode; break; + default: gcc_unreachable (); + } + else + /* The modes without ANY match the ALL modes. */ + full_cmp_mode = cmp_mode; + + if (swap_p) + { + rtx tmp = cmp2; + cmp2 = cmp1; + cmp1 = tmp; + } + + emit_insn (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, gen_rtx_SET ( + gen_rtx_REG (cmp_mode, CC_REGNUM), + gen_rtx_COMPARE (cmp_mode, cmp1, cmp2)), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_SCRATCH (scratch_mode))))); + emit_move_insn (target, const0_rtx); + emit_move_insn (tmp_reg, const1_rtx); + + emit_move_insn (target, + gen_rtx_IF_THEN_ELSE (SImode, + gen_rtx_fmt_ee (new_code, VOIDmode, + gen_rtx_REG (full_cmp_mode, CC_REGNUM), + const0_rtx), + target, tmp_reg)); +} + /* Generate a vector comparison expression loading either elements of THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 and CMP_OP2. */ @@ -5805,6 +6382,17 @@ s390_dwarf_frame_reg_mode (int regno) static const char * s390_mangle_type (const_tree type) { + type = TYPE_MAIN_VARIANT (type); + + if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE + && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) + return NULL; + + if (type == s390_builtin_types[BT_BV16QI]) return "U6__boolc"; + if (type == s390_builtin_types[BT_BV8HI]) return "U6__bools"; + if (type == s390_builtin_types[BT_BV4SI]) return "U6__booli"; + if (type == s390_builtin_types[BT_BV2DI]) return "U6__booll"; + if (TYPE_MAIN_VARIANT (type) == long_double_type_node && TARGET_LONG_DOUBLE_128) return "g"; @@ -10934,241 +11522,6 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) } } -/* Builtins. */ - -enum s390_builtin -{ - S390_BUILTIN_TBEGIN, - S390_BUILTIN_TBEGIN_NOFLOAT, - S390_BUILTIN_TBEGIN_RETRY, - S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, - S390_BUILTIN_TBEGINC, - S390_BUILTIN_TEND, - S390_BUILTIN_TABORT, - S390_BUILTIN_NON_TX_STORE, - S390_BUILTIN_TX_NESTING_DEPTH, - S390_BUILTIN_TX_ASSIST, - - S390_BUILTIN_S390_SFPC, - S390_BUILTIN_S390_EFPC, - - S390_BUILTIN_MAX -}; - -tree s390_builtin_decls[S390_BUILTIN_MAX]; - -static enum insn_code const code_for_builtin[S390_BUILTIN_MAX] = { - CODE_FOR_tbegin, - CODE_FOR_tbegin_nofloat, - CODE_FOR_tbegin_retry, - CODE_FOR_tbegin_retry_nofloat, - CODE_FOR_tbeginc, - CODE_FOR_tend, - CODE_FOR_tabort, - CODE_FOR_ntstg, - CODE_FOR_etnd, - CODE_FOR_tx_assist, - - CODE_FOR_s390_sfpc, - CODE_FOR_s390_efpc -}; - -static void -s390_init_builtins (void) -{ - tree ftype, uint64_type; - tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), - NULL, NULL); - tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); - - /* void foo (void) */ - ftype = build_function_type_list (void_type_node, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TBEGINC] = - add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC, - BUILT_IN_MD, NULL, NULL_TREE); - - /* void foo (int) */ - ftype = build_function_type_list (void_type_node, integer_type_node, - NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TABORT] = - add_builtin_function ("__builtin_tabort", ftype, - S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, - noreturn_attr); - s390_builtin_decls[S390_BUILTIN_TX_ASSIST] = - add_builtin_function ("__builtin_tx_assist", ftype, - S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE); - - /* void foo (unsigned) */ - ftype = build_function_type_list (void_type_node, unsigned_type_node, - NULL_TREE); - s390_builtin_decls[S390_BUILTIN_S390_SFPC] = - add_builtin_function ("__builtin_s390_sfpc", ftype, - S390_BUILTIN_S390_SFPC, BUILT_IN_MD, NULL, NULL_TREE); - - /* int foo (void *) */ - ftype = build_function_type_list (integer_type_node, ptr_type_node, - NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TBEGIN] = - add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN, - BUILT_IN_MD, NULL, returns_twice_attr); - s390_builtin_decls[S390_BUILTIN_TBEGIN_NOFLOAT] = - add_builtin_function ("__builtin_tbegin_nofloat", ftype, - S390_BUILTIN_TBEGIN_NOFLOAT, - BUILT_IN_MD, NULL, returns_twice_attr); - - /* int foo (void *, int) */ - ftype = build_function_type_list (integer_type_node, ptr_type_node, - integer_type_node, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TBEGIN_RETRY] = - add_builtin_function ("__builtin_tbegin_retry", ftype, - S390_BUILTIN_TBEGIN_RETRY, - BUILT_IN_MD, - NULL, returns_twice_attr); - s390_builtin_decls[S390_BUILTIN_TBEGIN_RETRY_NOFLOAT] = - add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype, - S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, - BUILT_IN_MD, - NULL, returns_twice_attr); - - /* int foo (void) */ - ftype = build_function_type_list (integer_type_node, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TX_NESTING_DEPTH] = - add_builtin_function ("__builtin_tx_nesting_depth", ftype, - S390_BUILTIN_TX_NESTING_DEPTH, - BUILT_IN_MD, NULL, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_TEND] = - add_builtin_function ("__builtin_tend", ftype, - S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE); - - /* unsigned foo (void) */ - ftype = build_function_type_list (unsigned_type_node, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_S390_EFPC] = - add_builtin_function ("__builtin_s390_efpc", ftype, - S390_BUILTIN_S390_EFPC, BUILT_IN_MD, NULL, NULL_TREE); - - /* void foo (uint64_t *, uint64_t) */ - if (TARGET_64BIT) - uint64_type = long_unsigned_type_node; - else - uint64_type = long_long_unsigned_type_node; - - ftype = build_function_type_list (void_type_node, - build_pointer_type (uint64_type), - uint64_type, NULL_TREE); - s390_builtin_decls[S390_BUILTIN_NON_TX_STORE] = - add_builtin_function ("__builtin_non_tx_store", ftype, - S390_BUILTIN_NON_TX_STORE, - BUILT_IN_MD, NULL, NULL_TREE); -} - -/* Expand an expression EXP that calls a built-in function, - with result going to TARGET if that's convenient - (and in mode MODE if that's convenient). - SUBTARGET may be used as the target for computing one of EXP's operands. - IGNORE is nonzero if the value is to be ignored. */ - -static rtx -s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - int ignore ATTRIBUTE_UNUSED) -{ -#define MAX_ARGS 2 - - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); - enum insn_code icode; - rtx op[MAX_ARGS], pat; - int arity; - bool nonvoid; - tree arg; - call_expr_arg_iterator iter; - - if (fcode >= S390_BUILTIN_MAX) - internal_error ("bad builtin fcode"); - icode = code_for_builtin[fcode]; - if (icode == 0) - internal_error ("bad builtin fcode"); - - if (!TARGET_HTM && fcode <= S390_BUILTIN_TX_ASSIST) - error ("Transactional execution builtins not enabled (-mhtm)\n"); - - /* Set a flag in the machine specific cfun part in order to support - saving/restoring of FPRs. */ - if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY) - cfun->machine->tbegin_p = true; - - nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; - - arity = 0; - FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) - { - const struct insn_operand_data *insn_op; - - if (arg == error_mark_node) - return NULL_RTX; - if (arity >= MAX_ARGS) - return NULL_RTX; - - insn_op = &insn_data[icode].operand[arity + nonvoid]; - - op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); - - if (!(*insn_op->predicate) (op[arity], insn_op->mode)) - { - if (insn_op->predicate == memory_operand) - { - /* Don't move a NULL pointer into a register. Otherwise - we have to rely on combine being able to move it back - in order to get an immediate 0 in the instruction. */ - if (op[arity] != const0_rtx) - op[arity] = copy_to_mode_reg (Pmode, op[arity]); - op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]); - } - else - op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); - } - - arity++; - } - - if (nonvoid) - { - machine_mode tmode = insn_data[icode].operand[0].mode; - if (!target - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - } - - switch (arity) - { - case 0: - pat = GEN_FCN (icode) (target); - break; - case 1: - if (nonvoid) - pat = GEN_FCN (icode) (target, op[0]); - else - pat = GEN_FCN (icode) (op[0]); - break; - case 2: - if (nonvoid) - pat = GEN_FCN (icode) (target, op[0], op[1]); - else - pat = GEN_FCN (icode) (op[0], op[1]); - break; - default: - gcc_unreachable (); - } - if (!pat) - return NULL_RTX; - emit_insn (pat); - - if (nonvoid) - return target; - else - return const0_rtx; -} /* Return the decl for the target specific builtin with the function code FCODE. */ @@ -13178,8 +13531,8 @@ s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, static void s390_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) { - tree sfpc = s390_builtin_decls[S390_BUILTIN_S390_SFPC]; - tree efpc = s390_builtin_decls[S390_BUILTIN_S390_EFPC]; + tree sfpc = s390_builtin_decls[S390_BUILTIN_s390_sfpc]; + tree efpc = s390_builtin_decls[S390_BUILTIN_s390_efpc]; tree call_efpc = build_call_expr (efpc, 0); tree fenv_var = create_tmp_var (unsigned_type_node); diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 9d151e6806c..6ddd8aa2052 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -111,22 +111,7 @@ enum processor_flags #define TARGET_TPF 0 /* Target CPU builtins. */ -#define TARGET_CPU_CPP_BUILTINS() \ - do \ - { \ - builtin_assert ("cpu=s390"); \ - builtin_assert ("machine=s390"); \ - builtin_define ("__s390__"); \ - if (TARGET_ZARCH) \ - builtin_define ("__zarch__"); \ - if (TARGET_64BIT) \ - builtin_define ("__s390x__"); \ - if (TARGET_LONG_DOUBLE_128) \ - builtin_define ("__LONG_DOUBLE_128__"); \ - if (TARGET_HTM) \ - builtin_define ("__HTM__"); \ - } \ - while (0) +#define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) #ifdef DEFAULT_TARGET_64BIT #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ @@ -989,4 +974,14 @@ extern const int processor_flags_table[]; always generate -1 in that case. */ #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) +/* Target pragma. */ + +/* resolve_overloaded_builtin can not be defined the normal way since + it is defined in code which technically belongs to the + front-end. */ +#define REGISTER_TARGET_PRAGMAS() \ + do { \ + s390_register_target_pragmas (); \ + } while (0) + #endif /* S390_H */ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e1188ba4f21..8c07d1bea57 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -126,21 +126,107 @@ UNSPEC_FPINT_NEARBYINT UNSPEC_FPINT_RINT + UNSPEC_LCBB + ; Vector - UNSPEC_VEC_EXTRACT - UNSPEC_VEC_SET - UNSPEC_VEC_PERM - UNSPEC_VEC_SRLB - UNSPEC_VEC_GENBYTEMASK - UNSPEC_VEC_VSUM - UNSPEC_VEC_VSUMG + UNSPEC_VEC_SMULT_HI + UNSPEC_VEC_UMULT_HI + UNSPEC_VEC_SMULT_LO UNSPEC_VEC_SMULT_EVEN UNSPEC_VEC_UMULT_EVEN UNSPEC_VEC_SMULT_ODD UNSPEC_VEC_UMULT_ODD + + UNSPEC_VEC_VMAL + UNSPEC_VEC_VMAH + UNSPEC_VEC_VMALH + UNSPEC_VEC_VMAE + UNSPEC_VEC_VMALE + UNSPEC_VEC_VMAO + UNSPEC_VEC_VMALO + + UNSPEC_VEC_GATHER + UNSPEC_VEC_EXTRACT + UNSPEC_VEC_INSERT_AND_ZERO + UNSPEC_VEC_LOAD_BNDRY UNSPEC_VEC_LOAD_LEN + UNSPEC_VEC_MERGEH + UNSPEC_VEC_MERGEL + UNSPEC_VEC_PACK + UNSPEC_VEC_PACK_SATURATE + UNSPEC_VEC_PACK_SATURATE_CC + UNSPEC_VEC_PACK_SATURATE_GENCC + UNSPEC_VEC_PACK_UNSIGNED_SATURATE + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC + UNSPEC_VEC_PERM + UNSPEC_VEC_PERMI + UNSPEC_VEC_EXTEND + UNSPEC_VEC_STORE_LEN + UNSPEC_VEC_UNPACKH + UNSPEC_VEC_UNPACKH_L + UNSPEC_VEC_UNPACKL + UNSPEC_VEC_UNPACKL_L + UNSPEC_VEC_ADDC + UNSPEC_VEC_ADDC_U128 + UNSPEC_VEC_ADDE_U128 + UNSPEC_VEC_ADDEC_U128 + UNSPEC_VEC_AVG + UNSPEC_VEC_AVGU + UNSPEC_VEC_CHECKSUM + UNSPEC_VEC_GFMSUM + UNSPEC_VEC_GFMSUM_128 + UNSPEC_VEC_GFMSUM_ACCUM + UNSPEC_VEC_GFMSUM_ACCUM_128 + UNSPEC_VEC_SET + + UNSPEC_VEC_VSUMG + UNSPEC_VEC_VSUMQ + UNSPEC_VEC_VSUM + UNSPEC_VEC_RL_MASK + UNSPEC_VEC_SLL + UNSPEC_VEC_SLB + UNSPEC_VEC_SLDB + UNSPEC_VEC_SRAL + UNSPEC_VEC_SRAB + UNSPEC_VEC_SRL + UNSPEC_VEC_SRLB + + UNSPEC_VEC_SUB_U128 + UNSPEC_VEC_SUBC + UNSPEC_VEC_SUBC_U128 + UNSPEC_VEC_SUBE_U128 + UNSPEC_VEC_SUBEC_U128 + + UNSPEC_VEC_TEST_MASK + + UNSPEC_VEC_VFAE + UNSPEC_VEC_VFAECC + + UNSPEC_VEC_VFEE + UNSPEC_VEC_VFEECC UNSPEC_VEC_VFENE UNSPEC_VEC_VFENECC + + UNSPEC_VEC_VISTR + UNSPEC_VEC_VISTRCC + + UNSPEC_VEC_VSTRC + UNSPEC_VEC_VSTRCCC + + UNSPEC_VEC_VCDGB + UNSPEC_VEC_VCDLGB + + UNSPEC_VEC_VCGDB + UNSPEC_VEC_VCLGDB + + UNSPEC_VEC_VFIDB + + UNSPEC_VEC_VLDEB + UNSPEC_VEC_VLEDB + + UNSPEC_VEC_VFTCIDB + UNSPEC_VEC_VFTCIDBCC ]) ;; @@ -651,7 +737,7 @@ ; Used with VFCMP to expand part of the mnemonic ; For fp we have a mismatch: eq in the insn name - e in asm (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) -(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVFH "h") (CCVFHE "he")]) +(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) (include "vector.md") @@ -10614,14 +10700,26 @@ ; Set and get floating point control register -(define_insn "s390_sfpc" +(define_insn "sfpc" [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] UNSPECV_SFPC)] "TARGET_HARD_FLOAT" "sfpc\t%0") -(define_insn "s390_efpc" +(define_insn "efpc" [(set (match_operand:SI 0 "register_operand" "=d") (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] "TARGET_HARD_FLOAT" "efpc\t%0") + + +; Load count to block boundary + +(define_insn "lcbb" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR") + (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z13" + "lcbb\t%0,%1,%b2" + [(set_attr "op_type" "VRX")]) diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt index 0ff897bf2fd..b841c4dac4d 100644 --- a/gcc/config/s390/s390.opt +++ b/gcc/config/s390/s390.opt @@ -153,6 +153,10 @@ mmvcle Target Report Mask(MVCLE) mvcle use +mzvector +Target Report Mask(ZVECTOR) +Enable the z vector language extension providing the context-sensitive vector macro. + mwarn-dynamicstack Target RejectNegative Var(s390_warn_dynamicstack_p) Warn if a function uses alloca or creates an array with dynamic size diff --git a/gcc/config/s390/s390intrin.h b/gcc/config/s390/s390intrin.h index 0f78136fb5a..c25f69ef71a 100644 --- a/gcc/config/s390/s390intrin.h +++ b/gcc/config/s390/s390intrin.h @@ -29,5 +29,8 @@ along with GCC; see the file COPYING3. If not see #include #endif +#ifdef __VEC__ +#include +#endif #endif /* _S390INTRIN_H*/ diff --git a/gcc/config/s390/t-s390 b/gcc/config/s390/t-s390 new file mode 100644 index 00000000000..800412c9dd2 --- /dev/null +++ b/gcc/config/s390/t-s390 @@ -0,0 +1,27 @@ +# Copyright (C) 2015 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +TM_H += $(srcdir)/config/s390/s390-builtins.def +TM_H += $(srcdir)/config/s390/s390-builtin-types.def + +s390-c.o: $(srcdir)/config/s390/s390-c.c \ + $(srcdir)/config/s390/s390-protos.h $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(TREE_H) $(TM_P_H) $(FLAGS_H) $(C_COMMON_H) $(GGC_H) \ + $(TARGET_H) $(TARGET_DEF_H) $(CPPLIB_H) $(C_PRAGMA_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/s390/s390-c.c diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h new file mode 100644 index 00000000000..95851f45ff7 --- /dev/null +++ b/gcc/config/s390/vecintrin.h @@ -0,0 +1,311 @@ +/* GNU compiler hardware transactional execution intrinsics + Copyright (C) 2015 Free Software Foundation, Inc. + Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef _VECINTRIN_H +#define _VECINTRIN_H + +#ifdef __VEC__ + +#define __VFTCI_ZERO 1<<11 +#define __VFTCI_ZERO_N 1<<10 +#define __VFTCI_NORMAL 1<<9 +#define __VFTCI_NORMAL_N 1<<8 +#define __VFTCI_SUBNORMAL 1<<7 +#define __VFTCI_SUBNORMAL_N 1<<6 +#define __VFTCI_INF 1<<5 +#define __VFTCI_INF_N 1<<4 +#define __VFTCI_QNAN 1<<3 +#define __VFTCI_QNAN_N 1<<2 +#define __VFTCI_SNAN 1<<1 +#define __VFTCI_SNAN_N 1<<0 + +/* This also accepts a type for its parameter, so it is not enough + to #define vec_step to __builtin_vec_step. */ +#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0) + +static inline int +__lcbb(const void *ptr, int bndry) +{ + int code; + switch (bndry) + { + case 64: code = 0; break; + case 128: code = 1; break; + case 256: code = 2; break; + case 512: code = 3; break; + case 1024: code = 4; break; + case 2048: code = 5; break; + case 4096: code = 6; break; + default: return 0; + } + return __builtin_s390_lcbb (ptr, code); +} + +#define vec_all_nle(X, Y) vec_all_nge ((Y), (X)) +#define vec_all_nlt(X, Y) vec_all_ngt ((Y), (X)) +#define vec_any_nle(X, Y) vec_any_nge ((Y), (X)) +#define vec_any_nlt(X, Y) vec_any_ngt ((Y), (X)) +#define vec_genmask __builtin_s390_vgbm +#define vec_genmasks_8 __builtin_s390_vgmb +#define vec_genmasks_16 __builtin_s390_vgmh +#define vec_genmasks_32 __builtin_s390_vgmf +#define vec_genmasks_64 __builtin_s390_vgmg +#define vec_splat_u8 __builtin_s390_vlrepb +#define vec_splat_s8 __builtin_s390_vlrepb +#define vec_splat_u16 __builtin_s390_vlreph +#define vec_splat_s16 __builtin_s390_vlreph +#define vec_splat_u32 __builtin_s390_vlrepf +#define vec_splat_s32 __builtin_s390_vlrepf +#define vec_splat_u64 __builtin_s390_vlrepg +#define vec_splat_s64 __builtin_s390_vlrepg +#define vec_add_u128 __builtin_s390_vaq +#define vec_addc_u128 __builtin_s390_vaccq +#define vec_adde_u128 __builtin_s390_vacq +#define vec_addec_u128 __builtin_s390_vacccq +#define vec_checksum __builtin_s390_vcksm +#define vec_gfmsum_128 __builtin_s390_vgfmg +#define vec_gfmsum_accum_128 __builtin_s390_vgfmag +#define vec_subc_u128 __builtin_s390_vscbiq +#define vec_sube_u128 __builtin_s390_vsbiq +#define vec_subec_u128 __builtin_s390_vsbcbiq +#define vec_ceil(X) __builtin_s390_vfidb((X), 4, 6) +#define vec_roundp(X) __builtin_s390_vfidb((X), 4, 6) +#define vec_floor(X) __builtin_s390_vfidb((X), 4, 7) +#define vec_roundm(X) __builtin_s390_vfidb((X), 4, 7) +#define vec_trunc(X) __builtin_s390_vfidb((X), 4, 5) +#define vec_roundz(X) __builtin_s390_vfidb((X), 4, 5) +#define vec_roundc(X) __builtin_s390_vfidb((X), 4, 0) +#define vec_round(X) __builtin_s390_vfidb((X), 4, 4) +#define vec_madd __builtin_s390_vfmadb +#define vec_msub __builtin_s390_vfmsdb + +static inline int +vec_all_nan (__vector double a) +{ + int cc; + __builtin_s390_vftcidb (a, + __VFTCI_QNAN + | __VFTCI_QNAN_N + | __VFTCI_SNAN + | __VFTCI_SNAN_N, &cc); + return cc == 0 ? 1 : 0; +} + +static inline int +vec_all_numeric (__vector double a) +{ + int cc; + __builtin_s390_vftcidb (a, + __VFTCI_NORMAL + | __VFTCI_NORMAL_N + | __VFTCI_SUBNORMAL + | __VFTCI_SUBNORMAL_N, &cc); + return cc == 0 ? 1 : 0; +} + +static inline int +vec_any_nan (__vector double a) +{ + int cc; + __builtin_s390_vftcidb (a, + __VFTCI_QNAN + | __VFTCI_QNAN_N + | __VFTCI_SNAN + | __VFTCI_SNAN_N, &cc); + return cc != 3 ? 1 : 0; +} + +static inline int +vec_any_numeric (__vector double a) +{ + int cc; + __builtin_s390_vftcidb (a, + __VFTCI_NORMAL + | __VFTCI_NORMAL_N + | __VFTCI_SUBNORMAL + | __VFTCI_SUBNORMAL_N, &cc); + return cc != 3 ? 1 : 0; +} +#define vec_gather_element __builtin_s390_vec_gather_element +#define vec_xld2 __builtin_s390_vec_xld2 +#define vec_xlw4 __builtin_s390_vec_xlw4 +#define vec_splats __builtin_s390_vec_splats +#define vec_insert __builtin_s390_vec_insert +#define vec_promote __builtin_s390_vec_promote +#define vec_extract __builtin_s390_vec_extract +#define vec_insert_and_zero __builtin_s390_vec_insert_and_zero +#define vec_load_bndry __builtin_s390_vec_load_bndry +#define vec_load_pair __builtin_s390_vec_load_pair +#define vec_load_len __builtin_s390_vec_load_len +#define vec_mergeh __builtin_s390_vec_mergeh +#define vec_mergel __builtin_s390_vec_mergel +#define vec_pack __builtin_s390_vec_pack +#define vec_packs __builtin_s390_vec_packs +#define vec_packs_cc __builtin_s390_vec_packs_cc +#define vec_packsu __builtin_s390_vec_packsu +#define vec_packsu_u16 __builtin_s390_vec_packsu_u16 +#define vec_packsu_u32 __builtin_s390_vec_packsu_u32 +#define vec_packsu_u64 __builtin_s390_vec_packsu_u64 +#define vec_packsu_cc __builtin_s390_vec_packsu_cc +#define vec_perm __builtin_s390_vec_perm +#define vec_permi __builtin_s390_vec_permi +#define vec_splat __builtin_s390_vec_splat +#define vec_scatter_element __builtin_s390_vec_scatter_element +#define vec_sel __builtin_s390_vec_sel +#define vec_extend_s64 __builtin_s390_vec_extend_s64 +#define vec_xstd2 __builtin_s390_vec_xstd2 +#define vec_xstw4 __builtin_s390_vec_xstw4 +#define vec_store_len __builtin_s390_vec_store_len +#define vec_unpackh __builtin_s390_vec_unpackh +#define vec_unpackl __builtin_s390_vec_unpackl +#define vec_addc __builtin_s390_vec_addc +#define vec_and __builtin_s390_vec_and +#define vec_andc __builtin_s390_vec_andc +#define vec_avg __builtin_s390_vec_avg +#define vec_all_eqv16qi __builtin_vec_all_eqv16qi +#define vec_all_eqv8hi __builtin_vec_all_eqv8hi +#define vec_all_eqv4si __builtin_vec_all_eqv4si +#define vec_all_eqv2di __builtin_vec_all_eqv2di +#define vec_all_eqv2df __builtin_vec_all_eqv2df +#define vec_all_gev16qi __builtin_vec_all_gev16qi +#define vec_all_geuv16qi __builtin_vec_all_geuv16qi +#define vec_all_gev8hi __builtin_vec_all_gev8hi +#define vec_all_geuv8hi __builtin_vec_all_geuv8hi +#define vec_all_gev4si __builtin_vec_all_gev4si +#define vec_all_geuv4si __builtin_vec_all_geuv4si +#define vec_all_gev2di __builtin_vec_all_gev2di +#define vec_all_geuv2di __builtin_vec_all_geuv2di +#define vec_all_gev2df __builtin_vec_all_gev2df +#define vec_all_gtv2df __builtin_vec_all_gtv2df +#define vec_all_eq __builtin_s390_vec_all_eq +#define vec_all_ne __builtin_s390_vec_all_ne +#define vec_all_ge __builtin_s390_vec_all_ge +#define vec_all_gt __builtin_s390_vec_all_gt +#define vec_all_le __builtin_s390_vec_all_le +#define vec_all_lt __builtin_s390_vec_all_lt +#define vec_any_eqv16qi __builtin_vec_any_eqv16qi +#define vec_any_eqv8hi __builtin_vec_any_eqv8hi +#define vec_any_eqv4si __builtin_vec_any_eqv4si +#define vec_any_eqv2di __builtin_vec_any_eqv2di +#define vec_any_eqv2df __builtin_vec_any_eqv2df +#define vec_any_gev16qi __builtin_vec_any_gev16qi +#define vec_any_geuv16qi __builtin_vec_any_geuv16qi +#define vec_any_gev8hi __builtin_vec_any_gev8hi +#define vec_any_geuv8hi __builtin_vec_any_geuv8hi +#define vec_any_gev4si __builtin_vec_any_gev4si +#define vec_any_geuv4si __builtin_vec_any_geuv4si +#define vec_any_gev2di __builtin_vec_any_gev2di +#define vec_any_geuv2di __builtin_vec_any_geuv2di +#define vec_any_gev2df __builtin_vec_any_gev2df +#define vec_any_gtv2df __builtin_vec_any_gtv2df +#define vec_any_eq __builtin_s390_vec_any_eq +#define vec_any_ne __builtin_s390_vec_any_ne +#define vec_any_ge __builtin_s390_vec_any_ge +#define vec_any_gt __builtin_s390_vec_any_gt +#define vec_any_le __builtin_s390_vec_any_le +#define vec_any_lt __builtin_s390_vec_any_lt +#define vec_cmpeq __builtin_s390_vec_cmpeq +#define vec_cmpge __builtin_s390_vec_cmpge +#define vec_cmpgt __builtin_s390_vec_cmpgt +#define vec_cmple __builtin_s390_vec_cmple +#define vec_cmplt __builtin_s390_vec_cmplt +#define vec_cntlz __builtin_s390_vec_cntlz +#define vec_cnttz __builtin_s390_vec_cnttz +#define vec_xor __builtin_s390_vec_xor +#define vec_gfmsum __builtin_s390_vec_gfmsum +#define vec_gfmsum_accum __builtin_s390_vec_gfmsum_accum +#define vec_abs __builtin_s390_vec_abs +#define vec_max __builtin_s390_vec_max +#define vec_max_dbl __builtin_s390_vec_max_dbl +#define vec_min __builtin_s390_vec_min +#define vec_min_dbl __builtin_s390_vec_min_dbl +#define vec_mladd __builtin_s390_vec_mladd +#define vec_mhadd __builtin_s390_vec_mhadd +#define vec_meadd __builtin_s390_vec_meadd +#define vec_moadd __builtin_s390_vec_moadd +#define vec_mulh __builtin_s390_vec_mulh +#define vec_mule __builtin_s390_vec_mule +#define vec_mulo __builtin_s390_vec_mulo +#define vec_nor __builtin_s390_vec_nor +#define vec_or __builtin_s390_vec_or +#define vec_popcnt __builtin_s390_vec_popcnt +#define vec_rl __builtin_s390_vec_rl +#define vec_rli __builtin_s390_vec_rli +#define vec_rl_mask __builtin_s390_vec_rl_mask +#define vec_sll __builtin_s390_vec_sll +#define vec_slb __builtin_s390_vec_slb +#define vec_sld __builtin_s390_vec_sld +#define vec_sldw __builtin_s390_vec_sldw +#define vec_sral __builtin_s390_vec_sral +#define vec_srab __builtin_s390_vec_srab +#define vec_srl __builtin_s390_vec_srl +#define vec_srb __builtin_s390_vec_srb +#define vec_subc __builtin_s390_vec_subc +#define vec_sum2 __builtin_s390_vec_sum2 +#define vec_sum_u128 __builtin_s390_vec_sum_u128 +#define vec_sum4 __builtin_s390_vec_sum4 +#define vec_test_mask __builtin_s390_vec_test_mask +#define vec_find_any_eq_idx __builtin_s390_vec_find_any_eq_idx +#define vec_find_any_ne_idx __builtin_s390_vec_find_any_ne_idx +#define vec_find_any_eq_or_0_idx __builtin_s390_vec_find_any_eq_or_0_idx +#define vec_find_any_ne_or_0_idx __builtin_s390_vec_find_any_ne_or_0_idx +#define vec_find_any_eq __builtin_s390_vec_find_any_eq +#define vec_find_any_ne __builtin_s390_vec_find_any_ne +#define vec_find_any_eq_idx_cc __builtin_s390_vec_find_any_eq_idx_cc +#define vec_find_any_ne_idx_cc __builtin_s390_vec_find_any_ne_idx_cc +#define vec_find_any_eq_or_0_idx_cc __builtin_s390_vec_find_any_eq_or_0_idx_cc +#define vec_find_any_ne_or_0_idx_cc __builtin_s390_vec_find_any_ne_or_0_idx_cc +#define vec_find_any_eq_cc __builtin_s390_vec_find_any_eq_cc +#define vec_find_any_ne_cc __builtin_s390_vec_find_any_ne_cc +#define vec_cmpeq_idx __builtin_s390_vec_cmpeq_idx +#define vec_cmpeq_or_0_idx __builtin_s390_vec_cmpeq_or_0_idx +#define vec_cmpeq_idx_cc __builtin_s390_vec_cmpeq_idx_cc +#define vec_cmpeq_or_0_idx_cc __builtin_s390_vec_cmpeq_or_0_idx_cc +#define vec_cmpne_idx __builtin_s390_vec_cmpne_idx +#define vec_cmpne_or_0_idx __builtin_s390_vec_cmpne_or_0_idx +#define vec_cmpne_idx_cc __builtin_s390_vec_cmpne_idx_cc +#define vec_cmpne_or_0_idx_cc __builtin_s390_vec_cmpne_or_0_idx_cc +#define vec_cp_until_zero __builtin_s390_vec_cp_until_zero +#define vec_cp_until_zero_cc __builtin_s390_vec_cp_until_zero_cc +#define vec_cmprg_idx __builtin_s390_vec_cmprg_idx +#define vec_cmpnrg_idx __builtin_s390_vec_cmpnrg_idx +#define vec_cmprg_or_0_idx __builtin_s390_vec_cmprg_or_0_idx +#define vec_cmpnrg_or_0_idx __builtin_s390_vec_cmpnrg_or_0_idx +#define vec_cmprg __builtin_s390_vec_cmprg +#define vec_cmpnrg __builtin_s390_vec_cmpnrg +#define vec_cmprg_idx_cc __builtin_s390_vec_cmprg_idx_cc +#define vec_cmpnrg_idx_cc __builtin_s390_vec_cmpnrg_idx_cc +#define vec_cmprg_or_0_idx_cc __builtin_s390_vec_cmprg_or_0_idx_cc +#define vec_cmpnrg_or_0_idx_cc __builtin_s390_vec_cmpnrg_or_0_idx_cc +#define vec_cmprg_cc __builtin_s390_vec_cmprg_cc +#define vec_cmpnrg_cc __builtin_s390_vec_cmpnrg_cc +#define vec_all_nge __builtin_s390_vec_all_nge +#define vec_all_ngt __builtin_s390_vec_all_ngt +#define vec_any_nge __builtin_s390_vec_any_nge +#define vec_any_ngt __builtin_s390_vec_any_ngt +#define vec_ctd __builtin_s390_vec_ctd +#define vec_ctd_s64 __builtin_s390_vec_ctd_s64 +#define vec_ctd_u64 __builtin_s390_vec_ctd_u64 +#define vec_ctsl __builtin_s390_vec_ctsl +#define vec_ctul __builtin_s390_vec_ctul +#define vec_ld2f __builtin_s390_vec_ld2f +#define vec_st2f __builtin_s390_vec_st2f +#endif /* __VEC__ */ +#endif /* _VECINTRIN_H */ diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index f07f5a70f18..16276e0de36 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -133,6 +133,8 @@ (VSTRING_FLAG_ZS 2) ; zero search (VSTRING_FLAG_CS 1)]) ; condition code set +(include "vx-builtins.md") + ; Full HW vector size moves (define_insn "mov" [(set (match_operand:V_128 0 "nonimmediate_operand" "=v, v,QR, v, v, v, v,v,d") diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md new file mode 100644 index 00000000000..e306ee8bd05 --- /dev/null +++ b/gcc/config/s390/vx-builtins.md @@ -0,0 +1,2081 @@ +;;- Instruction patterns for the System z vector facility builtins. +;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +; The patterns in this file are enabled with -mzvector + +(define_mode_iterator V_HW_64 [V2DI V2DF]) +(define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF]) +(define_mode_iterator VI_HW_SD [V4SI V2DI]) +(define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF]) +(define_mode_iterator VI_HW_HSD [V8HI V4SI V2DI]) + +; The element type of the vector with floating point modes translated +; to int modes of the same size. +(define_mode_attr non_vec_int[(V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI") + (V2HI "HI") (V4HI "HI") (V8HI "HI") + (V2SI "SI") (V4SI "SI") + (V2DI "DI") + (V2SF "SI") (V4SF "SI") + (V2DF "DI")]) + +; Condition code modes generated by int comparisons +(define_mode_iterator VICMP [CCVEQ CCVH CCVHU]) + +; Comparisons supported by the vec_cmp* builtins +(define_code_iterator intcmp [eq gt gtu ge geu lt ltu le leu]) +(define_code_iterator fpcmp [eq gt ge lt le]) + +; Comparisons supported by the vec_all/any* builtins +(define_code_iterator intcmpcc [eq ne gt ge lt le gtu geu ltu leu]) +(define_code_iterator fpcmpcc [eq ne gt ge unle unlt lt le]) + +; Flags for vector string instructions (vfae all 4, vfee only ZS and CS, vstrc all 4) +(define_constants + [(VSTRING_FLAG_IN 8) ; invert result + (VSTRING_FLAG_RT 4) ; result type + (VSTRING_FLAG_ZS 2) ; zero search + (VSTRING_FLAG_CS 1)]) ; condition code set + +; Rounding modes as being used for e.g. VFI +(define_constants + [(VEC_RND_CURRENT 0) + (VEC_RND_NEAREST_AWAY_FROM_ZERO 1) + (VEC_RND_SHORT_PREC 3) + (VEC_RND_NEAREST_TO_EVEN 4) + (VEC_RND_TO_ZERO 5) + (VEC_RND_TO_INF 6) + (VEC_RND_TO_MINF 7)]) + + +; Vector gather element + +(define_insn "vec_gather_element" + [(set (match_operand:V_HW_32_64 0 "register_operand" "=v") + (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") + (match_operand: 2 "register_operand" "v") + (match_operand:BLK 3 "memory_operand" "QR") + (match_operand:QI 4 "immediate_operand" "C")] + UNSPEC_VEC_GATHER))] + "TARGET_VX" + "vge\t%0,%O3(%v2,%R3),%b4" + [(set_attr "op_type" "VRV")]) + +(define_expand "vec_genmask" + [(match_operand:VI_HW 0 "register_operand" "=v") + (match_operand:QI 1 "immediate_operand" "C") + (match_operand:QI 2 "immediate_operand" "C")] + "TARGET_VX" +{ + int nunits = GET_MODE_NUNITS (mode); + int bitlen = GET_MODE_UNIT_BITSIZE (mode); + /* To bit little endian style. */ + int end = bitlen - 1 - INTVAL (operands[1]); + int start = bitlen - 1 - INTVAL (operands[2]); + rtx const_vec[16]; + int i; + unsigned HOST_WIDE_INT mask; + bool swapped_p = false; + + if (start > end) + { + i = start - 1; start = end + 1; end = i; + swapped_p = true; + } + if (end == 63) + mask = HOST_WIDE_INT_M1U; + else + mask = (HOST_WIDE_INT_1U << (end + 1)) - 1; + + mask &= ~((HOST_WIDE_INT_1U << start) - 1); + + if (swapped_p) + mask = ~mask; + + for (i = 0; i < nunits; i++) + const_vec[i] = GEN_INT (trunc_int_for_mode (mask, + GET_MODE_INNER (mode))); + + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_CONST_VECTOR (mode, + gen_rtvec_v (nunits, const_vec)))); + DONE; +}) + +(define_expand "vec_genbytemaskv16qi" + [(match_operand:V16QI 0 "register_operand" "") + (match_operand 1 "immediate_operand" "")] + "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'K', \"K\")" +{ + int i; + unsigned mask = 0x8000; + rtx const_vec[16]; + unsigned HOST_WIDE_INT byte_mask = INTVAL (operands[1]); + + for (i = 0; i < 16; i++) + { + if (mask & byte_mask) + const_vec[i] = constm1_rtx; + else + const_vec[i] = const0_rtx; + mask = mask >> 1; + } + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_CONST_VECTOR (V16QImode, + gen_rtvec_v (16, const_vec)))); + DONE; +}) + +(define_expand "vec_splats" + [(set (match_operand:V_HW 0 "register_operand" "") + (vec_duplicate:V_HW (match_operand: 1 "general_operand" "")))] + "TARGET_VX") + +(define_expand "vec_insert" + [(set (match_operand:V_HW 0 "register_operand" "") + (unspec:V_HW [(match_operand: 2 "register_operand" "") + (match_operand:SI 3 "shift_count_or_setmem_operand" "") + (match_operand:V_HW 1 "register_operand" "")] + UNSPEC_VEC_SET))] + "TARGET_VX" + "") + +; This is vec_set + modulo arithmetic on the element selector (op 2) +(define_expand "vec_promote" + [(set (match_operand:V_HW 0 "register_operand" "") + (unspec:V_HW [(match_operand: 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "") + (match_dup 0)] + UNSPEC_VEC_SET))] + "TARGET_VX" + "") + +; vec_extract is also an RTL standard name -> vector.md + +(define_insn "vec_insert_and_zero" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand: 1 "memory_operand" "QR")] + UNSPEC_VEC_INSERT_AND_ZERO))] + "TARGET_VX" + "vllez\t%v0,%1" + [(set_attr "op_type" "VRX")]) + +(define_insn "vlbb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "QR") + (match_operand:HI 2 "immediate_operand" " K")] + UNSPEC_VEC_LOAD_BNDRY))] + "TARGET_VX" + "vlbb\t%v0,%1,%2" + [(set_attr "op_type" "VRX")]) + +; FIXME: The following two patterns might using vec_merge. But what is +; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge +; (vec_select op0) (vec_select op1) +(define_insn "vec_mergeh" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand:V_HW 2 "register_operand" "v")] + UNSPEC_VEC_MERGEH))] + "TARGET_VX" + "vmrh\t%v0,%1,%2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_mergel" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand:V_HW 2 "register_operand" "v")] + UNSPEC_VEC_MERGEL))] + "TARGET_VX" + "vmrl\t%v0,%1,%2" + [(set_attr "op_type" "VRR")]) + + +; Vector pack + +(define_insn "vec_pack" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK))] + "TARGET_VX" + "vpk\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector pack saturate + +(define_insn "vec_packs" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK_SATURATE))] + "TARGET_VX" + "vpks\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; This is vec_packs_cc + loading cc into a caller specified memory location. +(define_expand "vec_packs_cc" + [(parallel + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "") + (match_operand:VI_HW_HSD 2 "register_operand" "")] + UNSPEC_VEC_PACK_SATURATE_GENCC)) + (set (match_operand: 0 "register_operand" "") + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_PACK_SATURATE_CC))]) + (set (match_dup 4) + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) + (set (match_operand:SI 3 "memory_operand" "") + (match_dup 4))] + "TARGET_VX" +{ + operands[4] = gen_reg_rtx (SImode); +}) + +(define_insn "*vec_packs_cc" + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK_SATURATE_GENCC)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_PACK_SATURATE_CC))] + "TARGET_VX" + "vpkss\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector pack logical saturate + +(define_insn "vec_packsu" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE))] + "TARGET_VX" + "vpkls\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; Emulate saturate unsigned pack on signed operands. +; Zero out negative elements and continue with the unsigned saturating pack. +(define_expand "vec_packsu_u" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE))] + "TARGET_VX" +{ + rtx null_vec = CONST0_RTX(mode); + machine_mode half_mode; + switch (mode) + { + case V8HImode: half_mode = V16QImode; break; + case V4SImode: half_mode = V8HImode; break; + case V2DImode: half_mode = V4SImode; break; + default: gcc_unreachable (); + } + s390_expand_vcond (operands[1], operands[1], null_vec, + GE, operands[1], null_vec); + s390_expand_vcond (operands[2], operands[2], null_vec, + GE, operands[2], null_vec); + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_UNSPEC (half_mode, + gen_rtvec (2, operands[1], operands[2]), + UNSPEC_VEC_PACK_UNSIGNED_SATURATE))); + DONE; +}) + +; This is vec_packsu_cc + loading cc into a caller specified memory location. +; FIXME: The reg to target mem copy should be issued by reload?! +(define_expand "vec_packsu_cc" + [(parallel + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "") + (match_operand:VI_HW_HSD 2 "register_operand" "")] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC)) + (set (match_operand: 0 "register_operand" "") + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))]) + (set (match_dup 4) + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) + (set (match_operand:SI 3 "memory_operand" "") + (match_dup 4))] + "TARGET_VX" +{ + operands[4] = gen_reg_rtx (SImode); +}) + +(define_insn "*vec_packsu_cc" + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v") + (match_operand:VI_HW_HSD 2 "register_operand" "v")] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))] + "TARGET_VX" + "vpklss\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector permute + +; vec_perm is also RTL standard name, but we can only use it for V16QI + +(define_insn "vec_zperm" + [(set (match_operand:V_HW_HSD 0 "register_operand" "=v") + (unspec:V_HW_HSD [(match_operand:V_HW_HSD 1 "register_operand" "v") + (match_operand:V_HW_HSD 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_PERM))] + "TARGET_VX" + "vperm\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_permi" + [(set (match_operand:V_HW_64 0 "register_operand" "") + (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "") + (match_operand:V_HW_64 2 "register_operand" "") + (match_operand:QI 3 "immediate_operand" "")] + UNSPEC_VEC_PERMI))] + "TARGET_VX" +{ + HOST_WIDE_INT val = INTVAL (operands[3]); + operands[3] = GEN_INT ((val & 1) | (val & 2) << 1); +}) + +(define_insn "*vec_permi" + [(set (match_operand:V_HW_64 0 "register_operand" "=v") + (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v") + (match_operand:V_HW_64 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "C")] + UNSPEC_VEC_PERMI))] + "TARGET_VX" + "vpdi\t%v0,%v1,%v2,%b3" + [(set_attr "op_type" "VRR")]) + + +; Vector replicate + + +; Replicate from vector element +(define_expand "vec_splat" + [(set (match_operand:V_HW 0 "register_operand" "") + (vec_duplicate:V_HW (vec_select: + (match_operand:V_HW 1 "register_operand" "") + (parallel + [(match_operand:QI 2 "immediate_operand" "")]))))] + "TARGET_VX") + +; Vector scatter element + +; vscef, vsceg + +; A 64 bit target adress generated from 32 bit elements +(define_insn "vec_scatter_elementv4si_DI" + [(set (mem:SI + (plus:DI (zero_extend:DI + (unspec:SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:DI 3 "immediate_operand" "I")] + UNSPEC_VEC_EXTRACT)) + (match_operand:SI 2 "address_operand" "ZQ"))) + (unspec:SI [(match_operand:V4SI 0 "register_operand" "v") + (match_dup 3)] UNSPEC_VEC_EXTRACT))] + "TARGET_VX && TARGET_64BIT" + "vscef\t%v0,%O2(%v1,%R2),%3" + [(set_attr "op_type" "VRV")]) + +; A 31 bit target address is generated from 64 bit elements +(define_insn "vec_scatter_element_SI" + [(set (mem: + (plus:SI (subreg:SI + (unspec: [(match_operand:V_HW_64 1 "register_operand" "v") + (match_operand:DI 3 "immediate_operand" "I")] + UNSPEC_VEC_EXTRACT) 4) + (match_operand:SI 2 "address_operand" "ZQ"))) + (unspec: [(match_operand:V_HW_64 0 "register_operand" "v") + (match_dup 3)] UNSPEC_VEC_EXTRACT))] + "TARGET_VX && !TARGET_64BIT" + "vsce\t%v0,%O2(%v1,%R2),%3" + [(set_attr "op_type" "VRV")]) + +; Element size and target adress size is the same +(define_insn "vec_scatter_element_" + [(set (mem: + (plus: (unspec: + [(match_operand: 1 "register_operand" "v") + (match_operand:DI 3 "immediate_operand" "I")] + UNSPEC_VEC_EXTRACT) + (match_operand:DI 2 "address_operand" "ZQ"))) + (unspec: [(match_operand:V_HW_32_64 0 "register_operand" "v") + (match_dup 3)] UNSPEC_VEC_EXTRACT))] + "TARGET_VX" + "vsce\t%v0,%O2(%v1,%R2),%3" + [(set_attr "op_type" "VRV")]) + +; Depending on the address size we have to expand a different pattern. +; This however cannot be represented in s390-builtins.def so we do the +; multiplexing here in the expander. +(define_expand "vec_scatter_element" + [(match_operand:V_HW_32_64 0 "register_operand" "") + (match_operand: 1 "register_operand" "") + (match_operand 2 "address_operand" "") + (match_operand:DI 3 "immediate_operand" "")] + "TARGET_VX" +{ + if (TARGET_64BIT) + { + PUT_MODE (operands[2], DImode); + emit_insn ( + gen_vec_scatter_element_DI (operands[0], operands[1], + operands[2], operands[3])); + } + else + { + PUT_MODE (operands[2], SImode); + emit_insn ( + gen_vec_scatter_element_SI (operands[0], operands[1], + operands[2], operands[3])); + } + DONE; +}) + + +; Vector select + +; Operand 3 selects bits from either OP1 (0) or OP2 (1) + +; Comparison operator should not matter as long as we always use the same ?! + +; Operands 1 and 2 are swapped in order to match the altivec builtin. +; If operand 3 is a const_int bitmask this would be vec_merge +(define_expand "vec_sel" + [(set (match_operand:V_HW 0 "register_operand" "") + (if_then_else:V_HW + (eq (match_operand: 3 "register_operand" "") + (match_dup 4)) + (match_operand:V_HW 2 "register_operand" "") + (match_operand:V_HW 1 "register_operand" "")))] + "TARGET_VX" +{ + operands[4] = CONST0_RTX (mode); +}) + + +; Vector sign extend to doubleword + +; Sign extend of right most vector element to respective double-word +(define_insn "vec_extend" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_EXTEND))] + "TARGET_VX" + "vseg\t%v0,%1" + [(set_attr "op_type" "VRR")]) + + +; Vector store with length + +; Store bytes in OP1 from OP0 with the highest indexed byte to be +; stored from OP0 given by OP2 +(define_insn "vstl" + [(set (match_operand:BLK 2 "memory_operand" "=Q") + (unspec:BLK [(match_operand:V 0 "register_operand" "v") + (match_operand:SI 1 "register_operand" "d")] + UNSPEC_VEC_STORE_LEN))] + "TARGET_VX" + "vstl\t%v0,%1,%2" + [(set_attr "op_type" "VRS")]) + + +; Vector unpack high + +; vuphb, vuphh, vuphf +(define_insn "vec_unpackh" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_UNPACKH))] + "TARGET_VX" + "vuph\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + +; vuplhb, vuplhh, vuplhf +(define_insn "vec_unpackh_l" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_UNPACKH_L))] + "TARGET_VX" + "vuplh\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + + +; Vector unpack low + +; vuplb, vuplhw, vuplf +(define_insn "vec_unpackl" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_UNPACKL))] + "TARGET_VX" + "vupl\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + +; vupllb, vupllh, vupllf +(define_insn "vec_unpackl_l" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_UNPACKL_L))] + "TARGET_VX" + "vupll\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + + +; Vector add + +; vaq + +; zvector builtins uses V16QI operands. So replace the modes in order +; to map this to a TImode add. We have to keep the V16QI mode +; operands in the expander in order to allow some operand type +; checking when expanding the builtin. +(define_expand "vec_add_u128" + [(match_operand:V16QI 0 "register_operand" "") + (match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "")] + "TARGET_VX" +{ + rtx op0 = gen_rtx_SUBREG (TImode, operands[0], 0); + rtx op1 = gen_rtx_SUBREG (TImode, operands[1], 0); + rtx op2 = gen_rtx_SUBREG (TImode, operands[2], 0); + + emit_insn (gen_rtx_SET (op0, + gen_rtx_PLUS (TImode, op1, op2))); + DONE; +}) + +; Vector add compute carry + +(define_insn "vec_addc" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v")] + UNSPEC_VEC_ADDC))] + "TARGET_VX" + "vacc\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_addc_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VEC_ADDC_U128))] + "TARGET_VX" + "vaccq\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector add with carry + +(define_insn "vec_adde_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_ADDE_U128))] + "TARGET_VX" + "vacq\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; Vector add with carry compute carry + +(define_insn "vec_addec_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_ADDEC_U128))] + "TARGET_VX" + "vacccq\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; Vector and + +; The following two patterns allow mixed mode and's as required for the intrinsics. +(define_insn "and_av2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (and:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0) + (match_operand:V2DF 2 "register_operand" "v")))] + "TARGET_VX" + "vn\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "and_cv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (and:V2DF (match_operand:V2DF 1 "register_operand" "v") + (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))] + "TARGET_VX" + "vn\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector and with complement + +; vnc +(define_insn "vec_andc3" + [(set (match_operand:VT_HW 0 "register_operand" "=v") + (and:VT_HW (not:VT_HW (match_operand:VT_HW 2 "register_operand" "v")) + (match_operand:VT_HW 1 "register_operand" "v")))] + "TARGET_VX" + "vnc\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; The following two patterns allow mixed mode and's as required for the intrinsics. +(define_insn "vec_andc_av2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (and:V2DF (not:V2DF (match_operand:V2DF 2 "register_operand" "v")) + (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)))] + + "TARGET_VX" + "vnc\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_andc_cv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (and:V2DF (not:V2DF (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)) + (match_operand:V2DF 1 "register_operand" "v")))] + "TARGET_VX" + "vnc\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector average + +(define_insn "vec_avg" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v")] + UNSPEC_VEC_AVG))] + "TARGET_VX" + "vavg\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; Vector average logical + +(define_insn "vec_avgu" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v")] + UNSPEC_VEC_AVGU))] + "TARGET_VX" + "vavgl\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector checksum + +(define_insn "vec_checksum" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VEC_CHECKSUM))] + "TARGET_VX" + "vcksm\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +;; +;; Vector compare +;; + +; vec_all/any int compares + +(define_expand "vec_all_" + [(match_operand:SI 0 "register_operand" "") + (intcmpcc (match_operand:VI_HW 1 "register_operand" "") + (match_operand:VI_HW 2 "register_operand" ""))] + "TARGET_VX" +{ + s390_expand_vec_compare_cc (operands[0], + , + operands[1], + operands[2], + true); + DONE; +}) + +(define_expand "vec_any_" + [(match_operand:SI 0 "register_operand" "") + (intcmpcc (match_operand:VI_HW 1 "register_operand" "") + (match_operand:VI_HW 2 "register_operand" ""))] + "TARGET_VX" +{ + s390_expand_vec_compare_cc (operands[0], + , + operands[1], + operands[2], + false); + DONE; +}) + +; vec_all/any fp compares + +(define_expand "vec_all_v2df" + [(match_operand:SI 0 "register_operand" "") + (fpcmpcc (match_operand:V2DF 1 "register_operand" "") + (match_operand:V2DF 2 "register_operand" ""))] + "TARGET_VX" +{ + s390_expand_vec_compare_cc (operands[0], + , + operands[1], + operands[2], + true); + DONE; +}) + +(define_expand "vec_any_v2df" + [(match_operand:SI 0 "register_operand" "") + (fpcmpcc (match_operand:V2DF 1 "register_operand" "") + (match_operand:V2DF 2 "register_operand" ""))] + "TARGET_VX" +{ + s390_expand_vec_compare_cc (operands[0], + , + operands[1], + operands[2], + false); + DONE; +}) + + +; Compare without generating CC + +(define_expand "vec_cmp" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (intcmp:VI_HW (match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v")))] + "TARGET_VX" +{ + s390_expand_vec_compare (operands[0], , operands[1], operands[2]); + DONE; +}) + +(define_expand "vec_cmpv2df" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (fpcmp:V2DI (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "register_operand" "v")))] + "TARGET_VX" +{ + s390_expand_vec_compare (operands[0], , operands[1], operands[2]); + DONE; +}) + + +; Vector count leading zeros + +; vec_cntlz -> clz +; vec_cnttz -> ctz + +; Vector xor + +; vec_xor -> xor + +; The following two patterns allow mixed mode xor's as required for the intrinsics. +(define_insn "xor_av2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (xor:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0) + (match_operand:V2DF 2 "register_operand" "v")))] + "TARGET_VX" + "vx\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "xor_cv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (xor:V2DF (match_operand:V2DF 1 "register_operand" "v") + (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))] + "TARGET_VX" + "vx\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector Galois field multiply sum + +(define_insn "vec_gfmsum" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_GFMSUM))] + "TARGET_VX" + "vgfm\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_gfmsum_128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:V2DI 2 "register_operand" "v")] + UNSPEC_VEC_GFMSUM_128))] + "TARGET_VX" + "vgfmg\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_gfmsum_accum" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand: 3 "register_operand" "v")] + UNSPEC_VEC_GFMSUM_ACCUM))] + "TARGET_VX" + "vgfma\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_gfmsum_accum_128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:V2DI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_GFMSUM_ACCUM_128))] + "TARGET_VX" + "vgfmag\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; FIXME: vec_neg ? + +; Vector load positive: vec_abs -> abs +; Vector maximum vec_max -> smax, logical vec_max -> umax +; Vector maximum vec_min -> smin, logical vec_min -> umin + + +; Vector multiply and add high + +; vec_mladd -> vec_vmal +; vmalb, vmalh, vmalf, vmalg +(define_insn "vec_vmal" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v") + (match_operand:VI_HW 3 "register_operand" "v")] + UNSPEC_VEC_VMAL))] + "TARGET_VX" + "vmal\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vec_mhadd -> vec_vmah/vec_vmalh + +; vmahb; vmahh, vmahf, vmahg +(define_insn "vec_vmah" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v") + (match_operand:VI_HW 3 "register_operand" "v")] + UNSPEC_VEC_VMAH))] + "TARGET_VX" + "vmah\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vmalhb; vmalhh, vmalhf, vmalhg +(define_insn "vec_vmalh" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v") + (match_operand:VI_HW 3 "register_operand" "v")] + UNSPEC_VEC_VMALH))] + "TARGET_VX" + "vmalh\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vec_meadd -> vec_vmae/vec_vmale + +; vmaeb; vmaeh, vmaef, vmaeg +(define_insn "vec_vmae" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand: 3 "register_operand" "v")] + UNSPEC_VEC_VMAE))] + "TARGET_VX" + "vmae\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vmaleb; vmaleh, vmalef, vmaleg +(define_insn "vec_vmale" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand: 3 "register_operand" "v")] + UNSPEC_VEC_VMALE))] + "TARGET_VX" + "vmale\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vec_moadd -> vec_vmao/vec_vmalo + +; vmaob; vmaoh, vmaof, vmaog +(define_insn "vec_vmao" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand: 3 "register_operand" "v")] + UNSPEC_VEC_VMAO))] + "TARGET_VX" + "vmao\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + +; vmalob; vmaloh, vmalof, vmalog +(define_insn "vec_vmalo" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand: 3 "register_operand" "v")] + UNSPEC_VEC_VMALO))] + "TARGET_VX" + "vmalo\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; Vector multiply high + +; vec_mulh -> vec_smulh/vec_umulh + +; vmhb, vmhh, vmhf +(define_insn "vec_smulh" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SMULT_HI))] + "TARGET_VX" + "vmh\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; vmlhb, vmlhh, vmlhf +(define_insn "vec_umulh" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_UMULT_HI))] + "TARGET_VX" + "vmlh\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector multiply low + +; vec_mule -> vec_widen_umult_even/vec_widen_smult_even +; vec_mulo -> vec_widen_umult_odd/vec_widen_smult_odd + + +; Vector nor + +(define_insn "vec_nor3" + [(set (match_operand:VT_HW 0 "register_operand" "=v") + (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "v") + (match_operand:VT_HW 2 "register_operand" "v"))))] + "TARGET_VX" + "vno\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; The following two patterns allow mixed mode and's as required for the intrinsics. +(define_insn "vec_nor_av2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (not:V2DF (ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0) + (match_operand:V2DF 2 "register_operand" "v"))))] + "TARGET_VX" + "vno\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_nor_cv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (not:V2DF (ior:V2DF (match_operand:V2DF 1 "register_operand" "v") + (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0))))] + "TARGET_VX" + "vno\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector or + +; The following two patterns allow mixed mode or's as required for the intrinsics. +(define_insn "ior_av2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0) + (match_operand:V2DF 2 "register_operand" "v")))] + "TARGET_VX" + "vo\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "ior_cv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (ior:V2DF (match_operand:V2DF 1 "register_operand" "v") + (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))] + "TARGET_VX" + "vo\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector population count vec_popcnt -> popcount +; Vector element rotate left logical vec_rl -> vrotl, vec_rli -> rot + +; Vector element rotate and insert under mask + +; verimb, verimh, verimf, verimg +(define_insn "verim" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "0") + (match_operand:VI_HW 2 "register_operand" "v") + (match_operand:VI_HW 3 "register_operand" "v") + (match_operand:SI 4 "immediate_operand" "I")] + UNSPEC_VEC_RL_MASK))] + "TARGET_VX" + "verim\t%v0,%v2,%v3,%b4" + [(set_attr "op_type" "VRI")]) + + +; Vector shift left + +(define_insn "vec_sll" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SLL))] + "TARGET_VX" + "vsl\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector shift left by byte + +(define_insn "vec_slb" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand: 2 "register_operand" "v")] + UNSPEC_VEC_SLB))] + "TARGET_VX" + "vslb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector shift left double by byte + +(define_insn "vec_sld" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand:V_HW 2 "register_operand" "v") + (match_operand:DI 3 "immediate_operand" "C")] + UNSPEC_VEC_SLDB))] + "TARGET_VX" + "vsldb\t%v0,%v1,%v2,%b3" + [(set_attr "op_type" "VRI")]) + +(define_expand "vec_sldw" + [(set (match_operand:V_HW 0 "register_operand" "") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") + (match_operand:V_HW 2 "register_operand" "") + (match_operand:DI 3 "immediate_operand" "")] + UNSPEC_VEC_SLDB))] + "TARGET_VX" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) << 2); +}) + +; Vector shift right arithmetic + +(define_insn "vec_sral" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SRAL))] + "TARGET_VX" + "vsra\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector shift right arithmetic by byte + +(define_insn "vec_srab" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand: 2 "register_operand" "v")] + UNSPEC_VEC_SRAB))] + "TARGET_VX" + "vsrab\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector shift right logical + +(define_insn "vec_srl" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SRL))] + "TARGET_VX" + "vsrl\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector shift right logical by byte + +; Pattern definition in vector.md +(define_expand "vec_srb" + [(set (match_operand:V_HW 0 "register_operand" "") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") + (match_operand: 2 "register_operand" "")] + UNSPEC_VEC_SRLB))] + "TARGET_VX") + + +; Vector subtract + +(define_insn "vec_sub_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VEC_SUB_U128))] + "TARGET_VX" + "vsq\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector subtract compute borrow indication + +(define_insn "vec_subc" + [(set (match_operand:VI_HW 0 "register_operand" "=v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v")] + UNSPEC_VEC_SUBC))] + "TARGET_VX" + "vscbi\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "vec_subc_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VEC_SUBC_U128))] + "TARGET_VX" + "vscbiq\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + + +; Vector subtract with borrow indication + +(define_insn "vec_sube_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_SUBE_U128))] + "TARGET_VX" + "vsbiq\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; Vector subtract with borrow compute and borrow indication + +(define_insn "vec_subec_u128" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VEC_SUBEC_U128))] + "TARGET_VX" + "vsbcbiq\t%v0,%v1,%v2,%v3" + [(set_attr "op_type" "VRR")]) + + +; Vector sum across + +; Sum across DImode parts of the 1st operand and add the rightmost +; element of 2nd operand +; vsumgh, vsumgf +(define_expand "vec_sum2" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:VI_HW_HS 1 "register_operand" "") + (match_operand:VI_HW_HS 2 "register_operand" "")] + UNSPEC_VEC_VSUMG))] + "TARGET_VX") + +; vsumqh, vsumqf +(define_insn "vec_sum_u128" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:VI_HW_SD 1 "register_operand" "v") + (match_operand:VI_HW_SD 2 "register_operand" "v")] + UNSPEC_VEC_VSUMQ))] + "TARGET_VX" + "vsumq\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; vsumb, vsumh +(define_expand "vec_sum4" + [(set (match_operand:V4SI 0 "register_operand" "") + (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand" "") + (match_operand:VI_HW_QH 2 "register_operand" "")] + UNSPEC_VEC_VSUM))] + "TARGET_VX") + + +; Vector test under mask + +(define_expand "vec_test_mask_int" + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "") + (match_operand: 2 "register_operand" "")] + UNSPEC_VEC_TEST_MASK)) + (set (match_operand:SI 0 "register_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_insn "*vec_test_mask" + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v") + (match_operand: 1 "register_operand" "v")] + UNSPEC_VEC_TEST_MASK))] + "TARGET_VX" + "vtm\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + + +; Vector find any element equal + +; vfaeb, vfaeh, vfaef +; vfaezb, vfaezh, vfaezf +(define_insn "vfae" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:SI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFAE))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = INTVAL (operands[3]); + + if (flags & VSTRING_FLAG_ZS) + { + flags &= ~VSTRING_FLAG_ZS; + operands[3] = GEN_INT (flags); + return "vfaez\t%v0,%v1,%v2,%b3"; + } + return "vfae\t%v0,%v1,%v2,%b3"; +} +[(set_attr "op_type" "VRR")]) + +; vfaebs, vfaehs, vfaefs +; vfaezbs, vfaezhs, vfaezfs +(define_insn "*vfaes" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:SI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFAE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_VEC_VFAECC))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = INTVAL (operands[3]); + + if (flags & VSTRING_FLAG_ZS) + { + flags &= ~VSTRING_FLAG_ZS; + operands[3] = GEN_INT (flags); + return "vfaezs\t%v0,%v1,%v2,%b3"; + } + return "vfaes\t%v0,%v1,%v2,%b3"; +} + [(set_attr "op_type" "VRR")]) + +(define_expand "vfaez" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:SI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFAE))] + "TARGET_VX" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_ZS); +}) + +(define_expand "vfaes" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFAE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_VEC_VFAECC))]) + (set (match_operand:SI 4 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS); +}) + +(define_expand "vfaezs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFAE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_VEC_VFAECC))]) + (set (match_operand:SI 4 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS); +}) + + +; Vector find element equal + +; vfeebs, vfeehs, vfeefs +; vfeezbs, vfeezhs, vfeezfs +(define_insn "*vfees" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFEE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_VEC_VFEECC))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = INTVAL (operands[3]); + + gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); + flags &= ~VSTRING_FLAG_CS; + + if (flags == VSTRING_FLAG_ZS) + return "vfeezs\t%v0,%v1,%v2"; + return "vfees\t%v0,%v1,%v2,%b3"; +} + [(set_attr "op_type" "VRR")]) + +; vfeeb, vfeeh, vfeef +(define_insn "vfee" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (const_int 0)] + UNSPEC_VEC_VFEE))] + "TARGET_VX" + "vfee\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + +; vfeezb, vfeezh, vfeezf +(define_insn "vfeez" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (const_int VSTRING_FLAG_ZS)] + UNSPEC_VEC_VFEE))] + "TARGET_VX" + "vfeezs\t%v0,%v1,%v2,2" + [(set_attr "op_type" "VRR")]) + +(define_expand "vfees" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (const_int VSTRING_FLAG_CS)] + UNSPEC_VEC_VFEE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (const_int VSTRING_FLAG_CS)] + UNSPEC_VEC_VFEECC))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vfeezs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_dup 4)] + UNSPEC_VEC_VFEE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 4)] + UNSPEC_VEC_VFEECC))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS); +}) + +; Vector find element not equal + +; vfeneb, vfeneh, vfenef +(define_insn "vfene" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (const_int 0)] + UNSPEC_VEC_VFENE))] + "TARGET_VX" + "vfene\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + +; vec_vfenes can be found in vector.md since it is used for strlen + +; vfenezb, vfenezh, vfenezf +(define_insn "vfenez" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (const_int VSTRING_FLAG_ZS)] + UNSPEC_VEC_VFENE))] + "TARGET_VX" + "vfenez\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_expand "vfenes" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (const_int VSTRING_FLAG_CS)] + UNSPEC_VEC_VFENE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (const_int VSTRING_FLAG_CS)] + UNSPEC_VEC_VFENECC))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vfenezs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_dup 4)] + UNSPEC_VEC_VFENE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 4)] + UNSPEC_VEC_VFENECC))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS); +}) + +; Vector isolate string + +; vistrb, vistrh, vistrf +(define_insn "vistr" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_VISTR))] + "TARGET_VX" + "vistr\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + +; vistrbs, vistrhs, vistrfs +(define_insn "*vistrs" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")] + UNSPEC_VEC_VISTR)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1)] UNSPEC_VEC_VISTRCC))] + "TARGET_VX" + "vistrs\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_expand "vistrs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")] + UNSPEC_VEC_VISTR)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1)] + UNSPEC_VEC_VISTRCC))]) + (set (match_operand:SI 2 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + + +; Vector compare range + +; vstrcb, vstrch, vstrcf +; vstrczb, vstrczh, vstrczf +(define_insn "vstrc" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v") + (match_operand:SI 4 "immediate_operand" "C")] + UNSPEC_VEC_VSTRC))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = INTVAL (operands[4]); + + if (flags & VSTRING_FLAG_ZS) + { + flags &= ~VSTRING_FLAG_ZS; + operands[4] = GEN_INT (flags); + return "vstrcz\t%v0,%v1,%v2,%v3,%b4"; + } + return "vstrc\t%v0,%v1,%v2,%v3,%b4"; +} +[(set_attr "op_type" "VRR")]) + +; vstrcbs, vstrchs, vstrcfs +; vstrczbs, vstrczhs, vstrczfs +(define_insn "*vstrcs" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v") + (match_operand:SI 4 "immediate_operand" "C")] + UNSPEC_VEC_VSTRC)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4)] + UNSPEC_VEC_VSTRCCC))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = INTVAL (operands[4]); + + if (flags & VSTRING_FLAG_ZS) + { + flags &= ~VSTRING_FLAG_ZS; + operands[4] = GEN_INT (flags); + return "vstrczs\t%v0,%v1,%v2,%v3,%b4"; + } + return "vstrcs\t%v0,%v1,%v2,%v3,%b4"; +} + [(set_attr "op_type" "VRR")]) + +(define_expand "vstrcz" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v") + (match_operand:SI 4 "immediate_operand" "C")] + UNSPEC_VEC_VSTRC))] + "TARGET_VX" +{ + operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_ZS); +}) + +(define_expand "vstrcs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_operand:VI_HW_QHS 3 "register_operand" "") + (match_operand:SI 4 "immediate_operand" "C")] + UNSPEC_VEC_VSTRC)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4)] + UNSPEC_VEC_VSTRCCC))]) + (set (match_operand:SI 5 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS); +}) + +(define_expand "vstrczs" + [(parallel + [(set (match_operand:VI_HW_QHS 0 "register_operand" "") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") + (match_operand:VI_HW_QHS 2 "register_operand" "") + (match_operand:VI_HW_QHS 3 "register_operand" "") + (match_operand:SI 4 "immediate_operand" "C")] + UNSPEC_VEC_VSTRC)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4)] + UNSPEC_VEC_VSTRCCC))]) + (set (match_operand:SI 5 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX" +{ + operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS); +}) + + +; Signed V2DI -> V2DF conversion - inexact exception disabled +(define_insn "vec_di_to_df_s64" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "C")] + UNSPEC_VEC_VCDGB))] + "TARGET_VX" + "vcdgb\t%v0,%v1,4,%b2" + [(set_attr "op_type" "VRR")]) + +; The result needs to be multiplied with 2**-op2 +(define_expand "vec_ctd_s64" + [(set (match_operand:V2DF 0 "register_operand" "") + (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "") + (const_int 0)] ; According to current BFP rounding mode + UNSPEC_VEC_VCDGB)) + (use (match_operand:QI 2 "immediate_operand" "")) + (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))] + "TARGET_VX" +{ + REAL_VALUE_TYPE f; + rtx c; + + real_2expN (&f, -INTVAL (operands[2]), DFmode); + c = CONST_DOUBLE_FROM_REAL_VALUE (f, DFmode); + + operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); + operands[3] = force_reg (V2DFmode, operands[3]); +}) + +; Unsigned V2DI -> V2DF conversion - inexact exception disabled +(define_insn "vec_di_to_df_u64" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "C")] + UNSPEC_VEC_VCDLGB))] + "TARGET_VX" + "vcdlgb\t%v0,%v1,4,%b2" + [(set_attr "op_type" "VRR")]) + +; The result needs to be multiplied with 2**-op2 +(define_expand "vec_ctd_u64" + [(set (match_operand:V2DF 0 "register_operand" "") + (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "") + (const_int 0)] ; According to current BFP rounding mode + UNSPEC_VEC_VCDLGB)) + (use (match_operand:QI 2 "immediate_operand" "")) + (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))] + "TARGET_VX" +{ + REAL_VALUE_TYPE f; + rtx c; + + real_2expN (&f, -INTVAL (operands[2]), DFmode); + c = CONST_DOUBLE_FROM_REAL_VALUE (f, DFmode); + + operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); + operands[3] = force_reg (V2DFmode, operands[3]); +}) + + +; Signed V2DF -> V2DI conversion - inexact exception disabled +(define_insn "vec_df_to_di_s64" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "C")] + UNSPEC_VEC_VCGDB))] + "TARGET_VX" + "vcgdb\t%v0,%v1,4,%b2" + [(set_attr "op_type" "VRR")]) + +; The input needs to be multiplied with 2**op2 +(define_expand "vec_ctsl" + [(use (match_operand:QI 2 "immediate_operand" "")) + (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "") + (match_dup 3))) + (set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode + UNSPEC_VEC_VCGDB))] + "TARGET_VX" +{ + REAL_VALUE_TYPE f; + rtx c; + + real_2expN (&f, INTVAL (operands[2]), DFmode); + c = CONST_DOUBLE_FROM_REAL_VALUE (f, DFmode); + + operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); + operands[3] = force_reg (V2DFmode, operands[3]); + operands[4] = gen_reg_rtx (V2DFmode); +}) + +; Unsigned V2DF -> V2DI conversion - inexact exception disabled +(define_insn "vec_df_to_di_u64" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "C")] + UNSPEC_VEC_VCLGDB))] + "TARGET_VX" + "vclgdb\t%v0,%v1,4,%b2" + [(set_attr "op_type" "VRR")]) + +; The input needs to be multiplied with 2**op2 +(define_expand "vec_ctul" + [(use (match_operand:QI 2 "immediate_operand" "")) + (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "") + (match_dup 3))) + (set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode + UNSPEC_VEC_VCLGDB))] + "TARGET_VX" +{ + REAL_VALUE_TYPE f; + rtx c; + + real_2expN (&f, INTVAL (operands[2]), DFmode); + c = CONST_DOUBLE_FROM_REAL_VALUE (f, DFmode); + + operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); + operands[3] = force_reg (V2DFmode, operands[3]); + operands[4] = gen_reg_rtx (V2DFmode); +}) + +; Vector load fp integer - IEEE inexact exception is suppressed +(define_insn "vfidb" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "C") + (match_operand:QI 3 "immediate_operand" "C")] + UNSPEC_VEC_VFIDB))] + "TARGET_VX" + "vfidb\t%v0,%v1,%b2,%b3" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_ceil" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_RND_TO_INF)] + UNSPEC_VEC_VFIDB))] + "TARGET_VX") + +(define_expand "vec_floor" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_RND_TO_MINF)] + UNSPEC_VEC_VFIDB))] + "TARGET_VX") + +(define_expand "vec_trunc" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_RND_TO_ZERO)] + UNSPEC_VEC_VFIDB))] + "TARGET_VX") + +(define_expand "vec_roundc" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_RND_CURRENT)] + UNSPEC_VEC_VFIDB))] + "TARGET_VX") + +(define_expand "vec_round" + [(set (match_operand:V2DI 0 "register_operand" "") + (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_RND_NEAREST_TO_EVEN)] + UNSPEC_VEC_VFIDB))] + "TARGET_VX") + + +; Vector load lengthened - V4SF -> V2DF + +(define_insn "*vldeb" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unspec:V2DF [(match_operand:V4SF 1 "register_operand" "v")] + UNSPEC_VEC_VLDEB))] + "TARGET_VX" + "vldeb\t%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_ld2f" + [; Initialize a vector to all zeroes. FIXME: This should not be + ; necessary since all elements of the vector will be set anyway. + ; This is just to make it explicit to the data flow framework. + (set (match_dup 2) (match_dup 3)) + (set (match_dup 2) (unspec:V4SF [(match_operand:SF 1 "memory_operand" "") + (const_int 0) + (match_dup 2)] + UNSPEC_VEC_SET)) + (set (match_dup 2) (unspec:V4SF [(match_dup 4) + (const_int 2) + (match_dup 2)] + UNSPEC_VEC_SET)) + (set (match_operand:V2DF 0 "register_operand" "") + (unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VLDEB))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V4SFmode); + operands[3] = CONST0_RTX (V4SFmode); + operands[4] = adjust_address (operands[1], SFmode, 4); +}) + + +; Vector load rounded - V2DF -> V4SF + +(define_insn "*vledb" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "v")] + UNSPEC_VEC_VLEDB))] + "TARGET_VX" + "vledb\t%v0,%v1,0,0" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_st2f" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")] + UNSPEC_VEC_VLEDB)) + (set (match_operand:SF 1 "memory_operand" "") + (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT)) + (set (match_dup 3) + (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))] + "TARGET_VX" +{ + operands[2] = gen_reg_rtx (V4SFmode); + operands[3] = adjust_address (operands[1], SFmode, 4); +}) + + +; Vector load negated fp + +(define_expand "vec_nabs" + [(set (match_operand:V2DF 0 "register_operand" "") + (neg:V2DF (abs:V2DF (match_operand:V2DF 1 "register_operand" ""))))] + "TARGET_VX") + +; Vector square root fp vec_sqrt -> sqrt rtx standard name + +; Vector FP test data class immediate + +(define_insn "*vftcidb" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v") + (match_operand:SI 2 "immediate_operand" "J")] + UNSPEC_VEC_VFTCIDB)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))] + "TARGET_VX" + "vftcidb\t%v0,%v1,%x2" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vftcidb_cconly" + [(set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_operand:V2DF 1 "register_operand" "v") + (match_operand:SI 2 "immediate_operand" "J")] + UNSPEC_VEC_VFTCIDBCC)) + (clobber (match_scratch:V2DI 0 "=v"))] + "TARGET_VX" + "vftcidb\t%v0,%v1,%x2" + [(set_attr "op_type" "VRR")]) + +(define_expand "vftcidb" + [(parallel + [(set (match_operand:V2DF 0 "register_operand" "") + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "") + (match_operand:SI 2 "immediate_operand" "")] + UNSPEC_VEC_VFTCIDB)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +;; +;; Integer compares +;; + +; All comparisons which produce a CC need fully populated (VI_HW) +; vector arguments. Otherwise the any/all CCs would be just bogus. + +(define_insn "*vec_cmp_cconly" + [(set (reg:VICMP CC_REGNUM) + (compare:VICMP (match_operand:VI_HW 0 "register_operand" "v") + (match_operand:VI_HW 1 "register_operand" "v"))) + (clobber (match_scratch:VI_HW 2 "=v"))] + "TARGET_VX" + "vcs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +; FIXME: The following 2x3 definitions should be merged into 2 with +; VICMP like above but I could not find a way to set the comparison +; operator (eq) depending on the mode CCVEQ (mode_iterator). Or the +; other way around - setting the mode depending on the code +; (code_iterator). +(define_expand "vec_cmpeq_cc" + [(parallel + [(set (reg:CCVEQ CC_REGNUM) + (compare:CCVEQ (match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v"))) + (set (match_operand:VI_HW 0 "register_operand" "=v") + (eq:VI_HW (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vec_cmph_cc" + [(parallel + [(set (reg:CCVH CC_REGNUM) + (compare:CCVH (match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v"))) + (set (match_operand:VI_HW 0 "register_operand" "=v") + (gt:VI_HW (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVH CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vec_cmphl_cc" + [(parallel + [(set (reg:CCVHU CC_REGNUM) + (compare:CCVHU (match_operand:VI_HW 1 "register_operand" "v") + (match_operand:VI_HW 2 "register_operand" "v"))) + (set (match_operand:VI_HW 0 "register_operand" "=v") + (gtu:VI_HW (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVHU CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + + +(define_insn "*vec_cmpeq_cc" + [(set (reg:CCVEQ CC_REGNUM) + (compare:CCVEQ (match_operand:VI_HW 0 "register_operand" "v") + (match_operand:VI_HW 1 "register_operand" "v"))) + (set (match_operand:VI_HW 2 "register_operand" "=v") + (eq:VI_HW (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vceqs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmph_cc" + [(set (reg:CCVH CC_REGNUM) + (compare:CCVH (match_operand:VI_HW 0 "register_operand" "v") + (match_operand:VI_HW 1 "register_operand" "v"))) + (set (match_operand:VI_HW 2 "register_operand" "=v") + (gt:VI_HW (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vchs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmphl_cc" + [(set (reg:CCVHU CC_REGNUM) + (compare:CCVHU (match_operand:VI_HW 0 "register_operand" "v") + (match_operand:VI_HW 1 "register_operand" "v"))) + (set (match_operand:VI_HW 2 "register_operand" "=v") + (gtu:VI_HW (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vchls\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +;; +;; Floating point comparesg +;; + +(define_insn "*vec_cmpv2df_cconly" + [(set (reg:VFCMP CC_REGNUM) + (compare:VFCMP (match_operand:V2DF 0 "register_operand" "v") + (match_operand:V2DF 1 "register_operand" "v"))) + (clobber (match_scratch:V2DI 2 "=v"))] + "TARGET_VX" + "vfcdbs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +; FIXME: Merge the following 2x3 patterns with VFCMP +(define_expand "vec_cmpeqv2df_cc" + [(parallel + [(set (reg:CCVEQ CC_REGNUM) + (compare:CCVEQ (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "register_operand" "v"))) + (set (match_operand:V2DI 0 "register_operand" "=v") + (eq:V2DI (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vec_cmphv2df_cc" + [(parallel + [(set (reg:CCVH CC_REGNUM) + (compare:CCVH (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "register_operand" "v"))) + (set (match_operand:V2DI 0 "register_operand" "=v") + (gt:V2DI (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVH CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + +(define_expand "vec_cmphev2df_cc" + [(parallel + [(set (reg:CCVFHE CC_REGNUM) + (compare:CCVFHE (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "register_operand" "v"))) + (set (match_operand:V2DI 0 "register_operand" "=v") + (ge:V2DI (match_dup 1) (match_dup 2)))]) + (set (match_operand:SI 3 "memory_operand" "") + (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))] + "TARGET_VX") + + +(define_insn "*vec_cmpeqv2df_cc" + [(set (reg:CCVEQ CC_REGNUM) + (compare:CCVEQ (match_operand:V2DF 0 "register_operand" "v") + (match_operand:V2DF 1 "register_operand" "v"))) + (set (match_operand:V2DI 2 "register_operand" "=v") + (eq:V2DI (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vfcedbs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmphv2df_cc" + [(set (reg:CCVH CC_REGNUM) + (compare:CCVH (match_operand:V2DF 0 "register_operand" "v") + (match_operand:V2DF 1 "register_operand" "v"))) + (set (match_operand:V2DI 2 "register_operand" "=v") + (gt:V2DI (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vfchdbs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmphev2df_cc" + [(set (reg:CCVFHE CC_REGNUM) + (compare:CCVFHE (match_operand:V2DF 0 "register_operand" "v") + (match_operand:V2DF 1 "register_operand" "v"))) + (set (match_operand:V2DI 2 "register_operand" "=v") + (ge:V2DI (match_dup 0) (match_dup 1)))] + "TARGET_VX" + "vfchedbs\t%v2,%v0,%v1" + [(set_attr "op_type" "VRR")])