From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 12:44:01 +0000 (+0100)
Subject: add comment
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b1aec0c7784e79f017def99207ac1baae4a31a0;p=riscv-isa-sim.git

add comment
---

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 3116ebb..f5b049c 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -20,6 +20,9 @@ uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
     return std::max(wid1, wid2);
 }
 
+/* convenience routines to map from compact 8-bit to 16-bit format,
+ * for use in new VBLOCK format
+ */
 void sv_regmap_8to16(union sv_reg_csr_entry8 const& r8,
                      union sv_reg_csr_entry &r16)
 {