From: lkcl Date: Sat, 1 May 2021 08:57:44 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~1007 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b340e8b9f337b2437899ed9ac50309bec4afea6;p=libreriscv.git --- diff --git a/docs.mdwn b/docs.mdwn index e1e40263c..0bdef1267 100644 --- a/docs.mdwn +++ b/docs.mdwn @@ -12,7 +12,7 @@ construction of FSMs and arbitrary length pipelines. | Git Repo | Documentation | Description | Pypi | |----------|---------------|---------------|-------- -| [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | | +| [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | TBD | | [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | -- | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) | | [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | -- | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) | | [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure | [libresoc-openpower-isa](https://pypi.org/project/libresoc-openpower-isa/) |