From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 1 Oct 2019 02:57:26 +0000 (-0700)
Subject: Add -assert
X-Git-Tag: working-ls180~990^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b4408432073ec4d9a2b8995b8e08a5bf6175f39;p=yosys.git

Add -assert
---

diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index b602b74d7..3bb3a8eb0 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module