From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 00:55:12 +0000 (-0700)
Subject: Move `techmap abc_map.v` into map_luts
X-Git-Tag: working-ls180~881^2^2~219
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b52d6e29ccc95fd4d102d9a59bb34125521c648;p=yosys.git

Move `techmap abc_map.v` into map_luts
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d6ff91e13..a2ec6a9c9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -380,7 +380,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -393,6 +393,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
+				run("techmap -map +/xilinx/abc_map.v";
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else