From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Thu, 13 Aug 2020 14:30:03 +0000 (+0100)
Subject: intel_alm: fix typo in MISTRAL_MUL27X27 cell name
X-Git-Tag: working-ls180~327
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b534a203ae733c194415838259709dcf706c7bf;p=yosys.git

intel_alm: fix typo in MISTRAL_MUL27X27 cell name
---

diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v
index 7e72dab0d..45fdebb3f 100644
--- a/techlibs/intel_alm/common/dsp_sim.v
+++ b/techlibs/intel_alm/common/dsp_sim.v
@@ -1,5 +1,5 @@
 (* abc9_box *)
-module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
+module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
 
 // TODO: Cyclone 10 GX timings; the below are for Cyclone V
 specify