From: Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Date: Thu, 26 Jan 2017 03:21:49 +0000 (+0000)
Subject: vsx-elemrev-4.c: Change expected code generation to accept D-mode memory accesses.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b5de3cb71e0771ee5f1abe88ad63e7613699b66;p=gcc.git

vsx-elemrev-4.c: Change expected code generation to accept D-mode memory accesses.

2017-01-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/vsx-elemrev-4.c: Change expected code
	generation to accept D-mode memory accesses.

From-SVN: r244916
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6a3007331d0..99bec45d5a7 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* gcc.target/powerpc/vsx-elemrev-4.c: Change expected code
+	generation to accept D-mode memory accesses.
+
 2017-01-25  Martin Sebor  <msebor@redhat.com>
 
 	PR c++/71290
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
index a116316c174..f40946353e4 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
@@ -3,8 +3,11 @@
 /* { dg-options "-mcpu=power9 -O0" } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
-/* { dg-final { scan-assembler-times "lxvx" 40 } } */
-/* { dg-final { scan-assembler-times "stxvx" 40 } } */
+
+/* Following will match either lxv or lxvx, either stxv or stxvx.
+   This is purposeful as either is fine.  */
+/* { dg-final { scan-assembler-times "lxv" 40 } } */
+/* { dg-final { scan-assembler-times "stxv" 40 } } */
 
 #include <altivec.h>