From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 1 May 2019 07:57:26 +0000 (+0200)
Subject: Fix width detection of memory access with bit slice, fixes #974
X-Git-Tag: yosys-0.9~157^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b6a02d3a74dc0113d595c6d26a4436160e28a6f;p=yosys.git

Fix width detection of memory access with bit slice, fixes #974

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b3a2a84be..d4515babf 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -645,6 +645,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			if (!id_ast->children[0]->range_valid)
 				log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
 			this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
+			if (children.size() > 1)
+				range = children[1];
 		} else
 			log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
 		if (range) {