From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 19:03:38 +0000 (-0800)
Subject: xilinx: add delays to INV
X-Git-Tag: working-ls180~780^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b74e0fa45a93f23448215ef9148ddc7bcd78cd7;p=yosys.git

xilinx: add delays to INV
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 0896f3176..df3b554c1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -160,6 +160,9 @@ module INV(
     input I
 );
   assign O = !I;
+  specify
+    (I => O) = 127;
+  endspecify
 endmodule
 
 (* abc9_lut=1 *)