From: Lukasz Dalek <ldalek@antmicro.com>
Date: Tue, 19 May 2020 14:58:48 +0000 (+0200)
Subject: Support optional labels at the end of module definition
X-Git-Tag: working-ls180~446^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b81a1b80926138cf0c3fe6d88818b689be3121c;p=yosys.git

Support optional labels at the end of module definition

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 15c231f3b..6687a195e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -435,7 +435,7 @@ module:
 		mod->str = *$4;
 		append_attr(mod, $1);
 		delete $4;
-	} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
+	} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
 		if (port_stubs.size() != 0)
 			frontend_verilog_yyerror("Missing details for module port `%s'.",
 					port_stubs.begin()->first.c_str());