From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jul 2019 12:33:45 +0000 (+0100)
Subject: add code comments
X-Git-Tag: ls180-24jan2020~699
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b89856512a9d889ccce2355740cff030f1cddd6;p=ieee754fpu.git

add code comments
---

diff --git a/src/ieee754/fclass/fclass.py b/src/ieee754/fclass/fclass.py
index f50412c4..8a5ccdcc 100644
--- a/src/ieee754/fclass/fclass.py
+++ b/src/ieee754/fclass/fclass.py
@@ -48,7 +48,8 @@ class FPClassMod(Elaboratable):
         finite_nzero = Signal(reset_less=True)
         msbzero = Signal(reset_less=True)
         is_sig_nan = Signal(reset_less=True)
-        # XXX use *REAL* mantissa width to detect msb
+        # XXX use *REAL* mantissa width to detect msb.
+        # XXX do NOT use a1.m_msbzero because it has extra bitspace
         m.d.comb += msbzero.eq(a1.m[a1.rmw-1] == 0) # sigh, 1 extra msb bit
         m.d.comb += finite_nzero.eq(~a1.is_nan & ~a1.is_inf & ~a1.is_zero)
         m.d.comb += is_sig_nan.eq(a1.exp_128 & (msbzero) & (~a1.m_zero))