From: whitequark <cz@m-labs.hk>
Date: Sat, 3 Aug 2019 22:59:33 +0000 (+0000)
Subject: vendor.lattice_ice40: add missing signal indexing.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b8d8bfcdd2095e5160e233c645be211803c4a60;p=nmigen.git

vendor.lattice_ice40: add missing signal indexing.
---

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 74fc36f..6f1021a 100644
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -278,8 +278,8 @@ class LatticeICE40Platform(TemplatedPlatform):
                 elif pin.xdr == 2:
                     # Re-register both inputs before they enter fabric. This increases hold time
                     # to an entire cycle, and adds one cycle of latency.
-                    io_args.append(("o", "D_IN_0",  i0_ff))
-                    io_args.append(("o", "D_IN_1",  i1_ff))
+                    io_args.append(("o", "D_IN_0",  i0_ff[bit]))
+                    io_args.append(("o", "D_IN_1",  i1_ff[bit]))
             if "o" in pin.dir:
                 if pin.xdr < 2:
                     io_args.append(("i", "D_OUT_0", pin_o[bit]))
@@ -287,7 +287,7 @@ class LatticeICE40Platform(TemplatedPlatform):
                     # Re-register negedge output after it leaves fabric. This increases setup time
                     # to an entire cycle, and doesn't add latency.
                     io_args.append(("i", "D_OUT_0", pin_o0[bit]))
-                    io_args.append(("i", "D_OUT_1", o1_ff))
+                    io_args.append(("i", "D_OUT_1", o1_ff[bit]))
 
             if pin.dir in ("oe", "io"):
                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))