From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 19:45:40 +0000 (-0700)
Subject: Add CHANGELOG entry
X-Git-Tag: yosys-0.9~58^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b8f3a93ada563fbae62772b0bf642bb54170954;p=yosys.git

Add CHANGELOG entry
---

diff --git a/CHANGELOG b/CHANGELOG
index 4c38f6e6e..496a521be 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -19,6 +19,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "read_aiger" frontend
     - Extended "muxcover -mux{4,8,16}=<cost>"
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 
 
 Yosys 0.7 .. Yosys 0.8
@@ -32,7 +33,7 @@ Yosys 0.7 .. Yosys 0.8
     - Added "write_verilog -decimal"
     - Added "scc -set_attr"
     - Added "verilog_defines" command
-    - Remeber defines from one read_verilog to next
+    - Remember defines from one read_verilog to next
     - Added support for hierarchical defparam
     - Added FIRRTL back-end
     - Improved ABC default scripts