From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 17:20:45 +0000 (+0000) Subject: increase DFF RAM size slightly X-Git-Tag: LS180_RC3~169 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b93f0dea253c4fb1d64628632c93297197a346b;p=soclayout.git increase DFF RAM size slightly --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 310e3c5..6344194 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -239066,49 +239066,49 @@ attribute \src "ls180.v:4.1-10688.10" attribute \cells_not_processed 1 module \ls180 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 + wire width 6 $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 + wire width 6 $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 + wire width 6 $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 + wire width 6 $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 + wire width 6 $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 + wire width 6 $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 + wire width 6 $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 + wire width 6 $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 attribute \src "ls180.v:10144.1-10162.4" wire width 64 $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 attribute \src "ls180.v:10144.1-10162.4" @@ -239671,15 +239671,15 @@ module \ls180 wire $0\main_libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:154.12-154.74" + attribute \src "ls180.v:140.12-140.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:128.5-128.69" + attribute \src "ls180.v:133.5-133.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:132.5-132.72" + attribute \src "ls180.v:145.5-145.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:135.11-135.79" + attribute \src "ls180.v:148.11-148.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:143.12-143.78" + attribute \src "ls180.v:152.12-152.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -241126,7 +241126,7 @@ module \ls180 attribute \src "ls180.v:7511.1-10140.4" wire $0\main_wdata_consumed[0:0] attribute \src "ls180.v:10144.1-10162.4" - wire width 4 $0\memadr[3:0] + wire width 6 $0\memadr[5:0] attribute \src "ls180.v:10172.1-10190.4" wire width 4 $0\memadr_1[3:0] attribute \src "ls180.v:10200.1-10204.4" @@ -246338,49 +246338,49 @@ module \ls180 attribute \src "ls180.v:10314.45-10314.54" wire width 10 $memrd$\storage_7$ls180.v:10314$2850_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10146$1_ADDR + wire width 6 $memwr$\mem$ls180.v:10146$1_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10146$1_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10146$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10148$2_ADDR + wire width 6 $memwr$\mem$ls180.v:10148$2_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10148$2_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10148$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10150$3_ADDR + wire width 6 $memwr$\mem$ls180.v:10150$3_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10150$3_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10150$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10152$4_ADDR + wire width 6 $memwr$\mem$ls180.v:10152$4_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10152$4_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10152$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10154$5_ADDR + wire width 6 $memwr$\mem$ls180.v:10154$5_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10154$5_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10154$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10156$6_ADDR + wire width 6 $memwr$\mem$ls180.v:10156$6_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10156$6_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10156$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10158$7_ADDR + wire width 6 $memwr$\mem$ls180.v:10158$7_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10158$7_DATA attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10158$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem$ls180.v:10160$8_ADDR + wire width 6 $memwr$\mem$ls180.v:10160$8_ADDR attribute \src "ls180.v:0.0-0.0" wire width 64 $memwr$\mem$ls180.v:10160$8_DATA attribute \src "ls180.v:0.0-0.0" @@ -249991,24 +249991,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:1925.6-1925.18" wire \builder_wait - attribute \src "ls180.v:37.19-37.23" - wire width 3 input 33 \eint - attribute \src "ls180.v:157.12-157.18" + attribute \src "ls180.v:5.19-5.23" + wire width 3 input 1 \eint + attribute \src "ls180.v:127.12-127.18" wire width 3 \eint_1 - attribute \src "ls180.v:34.21-34.27" - wire width 16 output 30 \gpio_i - attribute \src "ls180.v:35.20-35.26" - wire width 16 output 31 \gpio_o - attribute \src "ls180.v:36.20-36.27" - wire width 16 output 32 \gpio_oe - attribute \src "ls180.v:7.14-7.21" - wire output 3 \i2c_scl - attribute \src "ls180.v:8.14-8.23" - wire output 4 \i2c_sda_i - attribute \src "ls180.v:9.14-9.23" - wire output 5 \i2c_sda_o - attribute \src "ls180.v:10.14-10.24" - wire output 6 \i2c_sda_oe + attribute \src "ls180.v:18.21-18.27" + wire width 16 output 14 \gpio_i + attribute \src "ls180.v:19.20-19.26" + wire width 16 output 15 \gpio_o + attribute \src "ls180.v:20.20-20.27" + wire width 16 output 16 \gpio_oe + attribute \src "ls180.v:10.14-10.21" + wire output 6 \i2c_scl + attribute \src "ls180.v:11.14-11.23" + wire output 7 \i2c_sda_i + attribute \src "ls180.v:12.14-12.23" + wire output 8 \i2c_sda_o + attribute \src "ls180.v:13.14-13.24" + wire output 9 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -250232,7 +250232,7 @@ module \ls180 attribute \src "ls180.v:242.6-242.44" wire \main_interface1_converted_interface_we attribute \src "ls180.v:174.12-174.32" - wire width 4 \main_libresocsim_adr + wire width 6 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error attribute \src "ls180.v:63.12-63.39" @@ -250279,71 +250279,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:125.12-125.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:154.12-154.66" + attribute \src "ls180.v:140.12-140.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:155.13-155.67" + attribute \src "ls180.v:141.13-141.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:156.13-156.68" + attribute \src "ls180.v:142.13-142.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:127.6-127.61" + attribute \src "ls180.v:132.6-132.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:128.5-128.62" + attribute \src "ls180.v:133.5-133.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:129.6-129.63" + attribute \src "ls180.v:134.6-134.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:130.6-130.64" + attribute \src "ls180.v:135.6-135.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:131.6-131.64" + attribute \src "ls180.v:144.6-144.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:132.5-132.65" + attribute \src "ls180.v:145.5-145.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:133.6-133.66" + attribute \src "ls180.v:146.6-146.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:134.6-134.67" + attribute \src "ls180.v:147.6-147.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:135.11-135.72" + attribute \src "ls180.v:148.11-148.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:136.12-136.73" + attribute \src "ls180.v:149.12-149.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:137.6-137.68" + attribute \src "ls180.v:150.6-150.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:142.13-142.68" + attribute \src "ls180.v:151.13-151.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:151.12-151.68" + attribute \src "ls180.v:160.12-160.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:148.6-148.65" + attribute \src "ls180.v:157.6-157.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:150.6-150.63" + attribute \src "ls180.v:159.6-159.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:149.6-149.64" + attribute \src "ls180.v:158.6-158.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:152.12-152.68" + attribute \src "ls180.v:161.12-161.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:143.12-143.70" + attribute \src "ls180.v:152.12-152.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:144.13-144.71" + attribute \src "ls180.v:153.13-153.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:145.6-145.65" + attribute \src "ls180.v:154.6-154.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:147.6-147.65" + attribute \src "ls180.v:156.6-156.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:146.6-146.64" + attribute \src "ls180.v:155.6-155.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:158.6-158.67" + attribute \src "ls180.v:128.6-128.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:160.6-160.68" + attribute \src "ls180.v:130.6-130.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:161.6-161.68" + attribute \src "ls180.v:131.6-131.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:159.6-159.68" + attribute \src "ls180.v:129.6-129.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:138.6-138.67" + attribute \src "ls180.v:136.6-136.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:140.6-140.68" + attribute \src "ls180.v:138.6-138.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:141.6-141.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso attribute \src "ls180.v:139.6-139.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:137.6-137.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -253550,7 +253550,7 @@ module \ls180 attribute \src "ls180.v:850.5-850.24" wire \main_wdata_consumed attribute \src "ls180.v:10143.11-10143.17" - wire width 4 \memadr + wire width 6 \memadr attribute \src "ls180.v:10171.11-10171.19" wire width 4 \memadr_1 attribute \src "ls180.v:10199.12-10199.18" @@ -253577,50 +253577,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:252.6-252.13" wire \por_clk - attribute \src "ls180.v:42.19-42.22" - wire width 2 output 38 \pwm - attribute \src "ls180.v:162.12-162.17" + attribute \src "ls180.v:23.19-23.22" + wire width 2 output 19 \pwm + attribute \src "ls180.v:143.12-143.17" wire width 2 \pwm_1 - attribute \src "ls180.v:11.13-11.23" - wire output 7 \sdcard_clk - attribute \src "ls180.v:12.14-12.26" - wire output 8 \sdcard_cmd_i - attribute \src "ls180.v:13.13-13.25" - wire output 9 \sdcard_cmd_o - attribute \src "ls180.v:14.13-14.26" - wire output 10 \sdcard_cmd_oe - attribute \src "ls180.v:15.20-15.33" - wire width 4 output 11 \sdcard_data_i - attribute \src "ls180.v:16.19-16.32" - wire width 4 output 12 \sdcard_data_o - attribute \src "ls180.v:17.13-17.27" - wire output 13 \sdcard_data_oe - attribute \src "ls180.v:22.20-22.27" - wire width 13 output 18 \sdram_a - attribute \src "ls180.v:31.19-31.27" - wire width 2 output 27 \sdram_ba - attribute \src "ls180.v:28.13-28.24" - wire output 24 \sdram_cas_n - attribute \src "ls180.v:30.13-30.22" - wire output 26 \sdram_cke - attribute \src "ls180.v:33.13-33.24" - wire output 29 \sdram_clock - attribute \src "ls180.v:153.6-153.19" + attribute \src "ls180.v:24.13-24.23" + wire output 20 \sdcard_clk + attribute \src "ls180.v:25.14-25.26" + wire output 21 \sdcard_cmd_i + attribute \src "ls180.v:26.13-26.25" + wire output 22 \sdcard_cmd_o + attribute \src "ls180.v:27.13-27.26" + wire output 23 \sdcard_cmd_oe + attribute \src "ls180.v:28.20-28.33" + wire width 4 output 24 \sdcard_data_i + attribute \src "ls180.v:29.19-29.32" + wire width 4 output 25 \sdcard_data_o + attribute \src "ls180.v:30.13-30.27" + wire output 26 \sdcard_data_oe + attribute \src "ls180.v:31.20-31.27" + wire width 13 output 27 \sdram_a + attribute \src "ls180.v:40.19-40.27" + wire width 2 output 36 \sdram_ba + attribute \src "ls180.v:37.13-37.24" + wire output 33 \sdram_cas_n + attribute \src "ls180.v:39.13-39.22" + wire output 35 \sdram_cke + attribute \src "ls180.v:42.13-42.24" + wire output 38 \sdram_clock + attribute \src "ls180.v:162.6-162.19" wire \sdram_clock_1 - attribute \src "ls180.v:29.13-29.23" - wire output 25 \sdram_cs_n - attribute \src "ls180.v:32.19-32.27" - wire width 2 output 28 \sdram_dm - attribute \src "ls180.v:23.21-23.31" - wire width 16 output 19 \sdram_dq_i - attribute \src "ls180.v:24.20-24.30" - wire width 16 output 20 \sdram_dq_o - attribute \src "ls180.v:25.13-25.24" - wire output 21 \sdram_dq_oe - attribute \src "ls180.v:27.13-27.24" - wire output 23 \sdram_ras_n - attribute \src "ls180.v:26.13-26.23" - wire output 22 \sdram_we_n + attribute \src "ls180.v:38.13-38.23" + wire output 34 \sdram_cs_n + attribute \src "ls180.v:41.19-41.27" + wire width 2 output 37 \sdram_dm + attribute \src "ls180.v:32.21-32.31" + wire width 16 output 28 \sdram_dq_i + attribute \src "ls180.v:33.20-33.30" + wire width 16 output 29 \sdram_dq_o + attribute \src "ls180.v:34.13-34.24" + wire output 30 \sdram_dq_oe + attribute \src "ls180.v:36.13-36.24" + wire output 32 \sdram_ras_n + attribute \src "ls180.v:35.13-35.23" + wire output 31 \sdram_we_n attribute \src "ls180.v:2674.6-2674.15" wire \sdrio_clk attribute \src "ls180.v:2675.6-2675.17" @@ -253759,22 +253759,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2683.6-2683.17" wire \sdrio_clk_9 - attribute \src "ls180.v:38.13-38.26" - wire output 34 \spimaster_clk - attribute \src "ls180.v:40.13-40.27" - wire output 36 \spimaster_cs_n - attribute \src "ls180.v:41.13-41.27" - wire input 37 \spimaster_miso - attribute \src "ls180.v:39.13-39.27" - wire output 35 \spimaster_mosi - attribute \src "ls180.v:18.13-18.26" - wire output 14 \spisdcard_clk - attribute \src "ls180.v:20.13-20.27" - wire output 16 \spisdcard_cs_n - attribute \src "ls180.v:21.13-21.27" - wire input 17 \spisdcard_miso - attribute \src "ls180.v:19.13-19.27" - wire output 15 \spisdcard_mosi + attribute \src "ls180.v:6.13-6.26" + wire output 2 \spimaster_clk + attribute \src "ls180.v:8.13-8.27" + wire output 4 \spimaster_cs_n + attribute \src "ls180.v:9.13-9.27" + wire input 5 \spimaster_miso + attribute \src "ls180.v:7.13-7.27" + wire output 3 \spimaster_mosi + attribute \src "ls180.v:14.13-14.26" + wire output 10 \spisdcard_clk + attribute \src "ls180.v:16.13-16.27" + wire output 12 \spisdcard_cs_n + attribute \src "ls180.v:17.13-17.27" + wire input 13 \spisdcard_miso + attribute \src "ls180.v:15.13-15.27" + wire output 11 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:250.6-250.15" @@ -253789,12 +253789,12 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:251.6-251.15" wire \sys_rst_1 - attribute \src "ls180.v:6.13-6.20" - wire input 2 \uart_rx - attribute \src "ls180.v:5.13-5.20" - wire output 1 \uart_tx + attribute \src "ls180.v:22.13-22.20" + wire input 18 \uart_rx + attribute \src "ls180.v:21.13-21.20" + wire output 17 \uart_tx attribute \src "ls180.v:10142.12-10142.15" - memory width 64 size 16 \mem + memory width 64 size 64 \mem attribute \src "ls180.v:10170.12-10170.17" memory width 64 size 16 \mem_1 attribute \src "ls180.v:10198.12-10198.19" @@ -268479,11 +268479,11 @@ module \ls180 attribute \src "ls180.v:5780.27-5780.59" cell $eq $eq$ls180.v:5780$1101 parameter \A_SIGNED 0 - parameter \A_WIDTH 26 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:4] + connect \A \builder_shared_adr [29:6] connect \B 1'0 connect \Y $eq$ls180.v:5780$1101_Y end @@ -272812,7 +272812,7 @@ module \ls180 end attribute \src "ls180.v:10164.33-10164.36" cell $memrd $memrd$\mem$ls180.v:10164$2768 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273046,7 +273046,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2852 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273059,7 +273059,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2853 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273072,7 +273072,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2854 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273085,7 +273085,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2855 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273098,7 +273098,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2856 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273111,7 +273111,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2857 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273124,7 +273124,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2858 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -273137,7 +273137,7 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$2859 - parameter \ABITS 4 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -282163,36 +282163,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 4'xxxx + assign $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 6'xxxxxx assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 4'xxxx + assign $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 6'xxxxxx assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 4'xxxx + assign $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 6'xxxxxx assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 4'xxxx + assign $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 6'xxxxxx assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 4'xxxx + assign $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 6'xxxxxx assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 4'xxxx + assign $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 6'xxxxxx assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 4'xxxx + assign $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 6'xxxxxx assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 4'xxxx + assign $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 6'xxxxxx assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr[3:0] \main_libresocsim_adr + assign $0\memadr[5:0] \main_libresocsim_adr attribute \src "ls180.v:10145.2-10146.65" switch \main_libresocsim_we [0] attribute \src "ls180.v:10145.6-10145.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000011111111 case @@ -282201,7 +282201,7 @@ module \ls180 switch \main_libresocsim_we [1] attribute \src "ls180.v:10147.6-10147.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000001111111100000000 case @@ -282210,7 +282210,7 @@ module \ls180 switch \main_libresocsim_we [2] attribute \src "ls180.v:10149.6-10149.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000111111110000000000000000 case @@ -282219,7 +282219,7 @@ module \ls180 switch \main_libresocsim_we [3] attribute \src "ls180.v:10151.6-10151.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000011111111000000000000000000000000 case @@ -282228,7 +282228,7 @@ module \ls180 switch \main_libresocsim_we [4] attribute \src "ls180.v:10153.6-10153.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000001111111100000000000000000000000000000000 case @@ -282237,7 +282237,7 @@ module \ls180 switch \main_libresocsim_we [5] attribute \src "ls180.v:10155.6-10155.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000111111110000000000000000000000000000000000000000 case @@ -282246,7 +282246,7 @@ module \ls180 switch \main_libresocsim_we [6] attribute \src "ls180.v:10157.6-10157.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000011111111000000000000000000000000000000000000000000000000 case @@ -282255,35 +282255,35 @@ module \ls180 switch \main_libresocsim_we [7] attribute \src "ls180.v:10159.6-10159.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 \main_libresocsim_adr assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr $0\memadr[3:0] - update $memwr$\mem$ls180.v:10146$1_ADDR $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:10146$1_ADDR $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 update $memwr$\mem$ls180.v:10146$1_DATA $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 update $memwr$\mem$ls180.v:10146$1_EN $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 - update $memwr$\mem$ls180.v:10148$2_ADDR $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 + update $memwr$\mem$ls180.v:10148$2_ADDR $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 update $memwr$\mem$ls180.v:10148$2_DATA $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 update $memwr$\mem$ls180.v:10148$2_EN $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 - update $memwr$\mem$ls180.v:10150$3_ADDR $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 + update $memwr$\mem$ls180.v:10150$3_ADDR $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 update $memwr$\mem$ls180.v:10150$3_DATA $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 update $memwr$\mem$ls180.v:10150$3_EN $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 - update $memwr$\mem$ls180.v:10152$4_ADDR $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 + update $memwr$\mem$ls180.v:10152$4_ADDR $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 update $memwr$\mem$ls180.v:10152$4_DATA $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 update $memwr$\mem$ls180.v:10152$4_EN $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 - update $memwr$\mem$ls180.v:10154$5_ADDR $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 + update $memwr$\mem$ls180.v:10154$5_ADDR $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 update $memwr$\mem$ls180.v:10154$5_DATA $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 update $memwr$\mem$ls180.v:10154$5_EN $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 - update $memwr$\mem$ls180.v:10156$6_ADDR $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 + update $memwr$\mem$ls180.v:10156$6_ADDR $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 update $memwr$\mem$ls180.v:10156$6_DATA $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 update $memwr$\mem$ls180.v:10156$6_EN $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 - update $memwr$\mem$ls180.v:10158$7_ADDR $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 + update $memwr$\mem$ls180.v:10158$7_ADDR $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 update $memwr$\mem$ls180.v:10158$7_DATA $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 update $memwr$\mem$ls180.v:10158$7_EN $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 - update $memwr$\mem$ls180.v:10160$8_ADDR $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 + update $memwr$\mem$ls180.v:10160$8_ADDR $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 update $memwr$\mem$ls180.v:10160$8_DATA $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 update $memwr$\mem$ls180.v:10160$8_EN $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 end @@ -283928,14 +283928,6 @@ module \ls180 sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:128.5-128.69" - process $proc$ls180.v:128$2900 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end attribute \src "ls180.v:1280.5-1280.54" process $proc$ls180.v:1280$3400 assign { } { } @@ -284096,14 +284088,6 @@ module \ls180 update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:132.5-132.72" - process $proc$ls180.v:132$2901 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end attribute \src "ls180.v:1320.5-1320.49" process $proc$ls180.v:1320$3420 assign { } { } @@ -284184,6 +284168,14 @@ module \ls180 sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end + attribute \src "ls180.v:133.5-133.69" + process $proc$ls180.v:133$2900 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end attribute \src "ls180.v:1330.5-1330.41" process $proc$ls180.v:1330$3430 assign { } { } @@ -284256,14 +284248,6 @@ module \ls180 update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:135.11-135.79" - process $proc$ls180.v:135$2902 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end attribute \src "ls180.v:1350.5-1350.55" process $proc$ls180.v:1350$3439 assign { } { } @@ -284400,6 +284384,14 @@ module \ls180 sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end + attribute \src "ls180.v:140.12-140.74" + process $proc$ls180.v:140$2901 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end attribute \src "ls180.v:1403.12-1403.52" process $proc$ls180.v:1403$3456 assign { } { } @@ -284488,12 +284480,12 @@ module \ls180 sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:143.12-143.78" - process $proc$ls180.v:143$2903 + attribute \src "ls180.v:145.5-145.72" + process $proc$ls180.v:145$2902 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init end attribute \src "ls180.v:1463.11-1463.47" @@ -284568,6 +284560,14 @@ module \ls180 sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end + attribute \src "ls180.v:148.11-148.79" + process $proc$ls180.v:148$2903 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end attribute \src "ls180.v:1481.12-1481.55" process $proc$ls180.v:1481$3476 assign { } { } @@ -284720,6 +284720,14 @@ module \ls180 sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end + attribute \src "ls180.v:152.12-152.78" + process $proc$ls180.v:152$2904 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end attribute \src "ls180.v:1520.11-1520.47" process $proc$ls180.v:1520$3495 assign { } { } @@ -284792,14 +284800,6 @@ module \ls180 sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:154.12-154.74" - process $proc$ls180.v:154$2904 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - sync init - end attribute \src "ls180.v:1540.5-1540.46" process $proc$ls180.v:1540$3504 assign { } { } @@ -294625,13 +294625,13 @@ module \ls180 end attribute \src "ls180.v:7511.1-10140.4" process $proc$ls180.v:7511$2434 - assign $0\uart_tx[0:0] \uart_tx - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } @@ -299178,13 +299178,13 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\uart_tx[0:0] 1'1 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 assign $0\pwm[1:0] 2'00 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 @@ -299470,13 +299470,13 @@ module \ls180 case end sync posedge \sys_clk_1 - update \uart_tx $0\uart_tx[0:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] @@ -300752,7 +300752,7 @@ module \ls180 connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [3:0] + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w connect \main_libresocsim_zero_trigger $ne$ls180.v:3000$84_Y