From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 21:57:38 +0000 (-0700)
Subject: Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
X-Git-Tag: working-ls180~1039^2~86
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b9b0fcd0630133092b23a18453eb420534b2369;p=yosys.git

Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
---

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 55aa72aa7..284bc90d0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -273,7 +273,9 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("opt_expr -fine", "               (if -dsp)");
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");