From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Apr 2021 15:07:42 +0000 (+0100)
Subject: add comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ba7d24f8e10a3a4c802c6f58f2f442a31636098;p=soc-cocotb-sim.git

add comments
---

diff --git a/ls180/pre_pnr/test.py b/ls180/pre_pnr/test.py
index b6dd38b..9abada1 100644
--- a/ls180/pre_pnr/test.py
+++ b/ls180/pre_pnr/test.py
@@ -302,8 +302,11 @@ def boundary_scan_run(dut):
 
 @cocotb.test()
 def wishbone_basic(dut):
-    """
-    Test of an added Wishbone interface
+    """Test of an added Wishbone interface
+
+    for this test the soc JTAG TAP address width is 29 bits and data is 64
+    JTAG has access to the *full* memory range, including peripherals,
+    as defined by the litex setup.
     """
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
@@ -323,6 +326,7 @@ def wishbone_basic(dut):
     yield master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
+    # WBaddresses in soc.debug.jtag.JTAG are 29 bits
     data_in.binstr = "00000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
@@ -332,6 +336,7 @@ def wishbone_basic(dut):
     yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
+    # data is 64-bit
     data_in.binstr = "01010101" * 8
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)