From: Luke Kenneth Casson Leighton Date: Mon, 9 May 2022 11:25:28 +0000 (+0100) Subject: remove SIM_DEVICES parameter temporarily which is not in X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bb221ae03b6daaf2c18e58771ab97bf45b06a80;p=nmigen.git remove SIM_DEVICES parameter temporarily which is not in v2016.2. https://gitlab.com/nmigen/nmigen/-/issues/4 --- diff --git a/examples/basic/ctr.py b/examples/basic/ctr.py index 044cc53..b663f8b 100644 --- a/examples/basic/ctr.py +++ b/examples/basic/ctr.py @@ -1,4 +1,4 @@ -from nmigen import * +from nmigen import Elaboratable, Signal, Module from nmigen.cli import main diff --git a/nmigen/vendor/xilinx.py b/nmigen/vendor/xilinx.py index 2e589fc..1005bd2 100644 --- a/nmigen/vendor/xilinx.py +++ b/nmigen/vendor/xilinx.py @@ -518,7 +518,6 @@ class XilinxPlatform(TemplatedPlatform): --json {{name}}.json --write {{name}}_routed.json --fasm {{name}}.fasm - --seed 1 {{get_override("nextpnr_opts")|options}} """, r""" @@ -698,14 +697,17 @@ class XilinxPlatform(TemplatedPlatform): ready = Signal() m.submodules += Instance(STARTUP_PRIMITIVE[self.family], o_EOS=ready) m.domains += ClockDomain("sync", reset_less=self.default_rst is None) + print ("family", self.family) if self.toolchain != "Vivado": m.submodules += Instance("BUFGCE", i_CE=ready, i_I=clk_i, o_O=ClockSignal("sync")) elif self.family == "series7": - # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes - # sim/synth mismatches with Vivado 2019.2, and the suggested workaround - # (SIM_DEVICE parameter) breaks Vivado 2017.4. + # Actually use BUFGCTRL configured as BUFGCE, since using + # BUFGCE causes sim/synth mismatches with Vivado 2019.2, + # and the suggested workaround (SIM_DEVICE parameter) breaks + # Vivado 2017.4. and Vivado v2016.2. + # XXX TODO: https://gitlab.com/nmigen/nmigen/-/issues/4 m.submodules += Instance("BUFGCTRL", - p_SIM_DEVICE="7SERIES", + # p_SIM_DEVICE="7SERIES", # removing. i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1), i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1), o_O=ClockSignal("sync")