From: Florent Kermarrec Date: Mon, 20 Jun 2016 14:00:19 +0000 (+0200) Subject: boards/targets/sim: desactivate refresh for simulation X-Git-Tag: 24jan2021_ls180~1938 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bb2bc35e2c0f82e3b3af260ce7b437c5bfba7f7;p=litex.git boards/targets/sim: desactivate refresh for simulation --- diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index c04e883a..9c892911 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -15,6 +15,7 @@ from litex.soc.integration.soc_core import mem_decoder from litedram.common import PhySettings from litedram.modules import IS42S16160 from litedram.phy.model import SDRAMPHYModel +from litedram.core.controller import ControllerSettings from liteeth.phy.model import LiteEthPHYModel from liteeth.core.mac import LiteEthMAC @@ -49,7 +50,8 @@ class BaseSoC(SoCSDRAM): self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, - sdram_module.timing_settings) + sdram_module.timing_settings, + ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)