From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 13 Sep 2020 11:39:33 +0000 (+0100)
Subject: clarify
X-Git-Tag: semi_working_ecp5~77
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bbcecc27997017e2f4df9b5ea708604fbdf9c94;p=soc.git

clarify
---

diff --git a/src/unused/TLB/ariane/plru.py b/src/unused/TLB/ariane/plru.py
index 70e21268..e99d56d9 100644
--- a/src/unused/TLB/ariane/plru.py
+++ b/src/unused/TLB/ariane/plru.py
@@ -23,8 +23,8 @@ class PLRU(Elaboratable):
     def __init__(self, BITS):
         self.BITS = BITS
         self.acc_en = Signal(BITS)
-        self.lru_o = Signal(BITS)
         self.acc_i = Signal()
+        self.lru_o = Signal(BITS)
 
     def elaborate(self, platform=None):
         m = Module()
@@ -49,7 +49,7 @@ class PLRU(Elaboratable):
         # endcase
 
         LOG_TLB = log2_int(self.BITS)
-        hit = Signal(self.BITS)
+        hit = Signal(self.BITS, reset_less=True)
         m.d.comb += hit.eq(Repl(self.acc_i, self.BITS) & self.acc_en)
 
         for i in range(self.BITS):