From: lkcl <lkcl@web>
Date: Sat, 11 Jun 2022 18:14:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1845
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bc52b7da93d1604aab523e1ab178447a58b16e4;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index d2667db86..1ca042148 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -3,9 +3,9 @@
 [[!toc]]
 
 SVP64 is designed around fundamental and inviolate RISC principles.
-This gives a uniformity and regularity to the ISA which was why RISC
-as a concept became popular. It is just that nobody has ever considered
-applying the RISC concept to a *Vector* ISA before.
+This gives a uniformity and regularity to the ISA, making implementation
+straightforward, which was why RISC
+as a concept became popular.
 
 1. There are no actual Vector instructions: Scalar instructions
    are the sole exclusive bedrock.