From: Lisa Hsu Date: Thu, 11 Mar 2004 23:52:29 +0000 (-0500) Subject: merge with m5 head X-Git-Tag: m5_1.0_tutorial~354 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bc8cffc75c2e03a6a8fe5f4425940a16405f672;p=gem5.git merge with m5 head --HG-- extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311 --- 3bc8cffc75c2e03a6a8fe5f4425940a16405f672 diff --cc dev/alpha_console.cc index ad9d0a239,04046557a..f592b239d --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@@ -50,11 -52,11 +53,12 @@@ using namespace std; - AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, - SimpleDisk *d, System *system, - BaseCPU *cpu, TsunamiIO *clock, int num_cpus, - Addr a, MemoryController *mmu) - : FunctionalMemory(name), disk(d), console(cons), addr(a) + AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, - System *system, BaseCPU *cpu, TlaserClock *clock, ++ System *system, BaseCPU *cpu, TsunamiIO *clock, + int num_cpus, MemoryController *mmu, Addr a, + HierParams *hier, Bus *bus) + : PioDevice(name), disk(d), console(cons), addr(a) ++>>>>>>> { mmu->add_child(this, Range(addr, addr + size)); @@@ -252,7 -266,9 +268,9 @@@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaCo Param addr; SimObjectParam system; SimObjectParam cpu; - SimObjectParam clock; + SimObjectParam clock; + SimObjectParam io_bus; + SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) diff --cc dev/alpha_console.hh index d0fa552af,b617b64e7..be8538e50 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@@ -35,9 -35,8 +35,9 @@@ #include "base/range.hh" #include "dev/alpha_access.h" - #include "mem/functional_mem/functional_memory.hh" + #include "dev/io_device.hh" #include "sim/host.hh" +#include "dev/tsunami_io.hh" class BaseCPU; class SimConsole; @@@ -89,10 -88,10 +89,10 @@@ class AlphaConsole : public PioDevic public: /** Standard Constructor */ - AlphaConsole(const std::string &name, SimConsole *cons, - SimpleDisk *d, System *system, BaseCPU *cpu, - TsunamiIO *clock, int num_cpus, - Addr a, MemoryController *mmu); + AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d, - System *system, BaseCPU *cpu, TlaserClock *clock, ++ System *system, BaseCPU *cpu, TsunamiIO *clock, + int num_cpus, MemoryController *mmu, Addr addr, + HierParams *hier, Bus *bus); /** * memory mapped reads and writes