From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Mon, 25 Feb 2019 06:37:52 +0000 (-0800)
Subject: Add reset logic
X-Git-Tag: div_pipeline~2370
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3be1e5f6abf6ee8844eb5421eb504b3682903f1a;p=soc.git

Add reset logic
---

diff --git a/TLB/src/CamEntry.py b/TLB/src/CamEntry.py
index cbb78d69..f8f43b7a 100644
--- a/TLB/src/CamEntry.py
+++ b/TLB/src/CamEntry.py
@@ -15,7 +15,7 @@ class CamEntry:
         self.key = Signal(key_size)
         
         # Input
-        self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reserve
+        self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reset
         self.key_in = Signal(key_size) # Reference key for the CAM
         self.data_in = Signal(data_size) # Data input when writing
         
@@ -27,6 +27,8 @@ class CamEntry:
     def elaborate(self, platform=None):
         m = Module()
         with m.Switch(self.command):
+            with m.Case("00"):
+                m.d.sync += self.match.eq(0)
             with m.Case("01"):
                 with m.If(self.key_in == self.key):
                     m.d.sync += self.match.eq(1)
@@ -39,6 +41,10 @@ class CamEntry:
                     self.match.eq(0)
                 ] 
             with m.Case():
-                m.d.sync += self.match.eq(0)
+                m.d.sync += [
+                    self.match.eq(0),
+                    self.data.eq(0),
+                    self.key.eq(0)
+                ]
         
         return m
diff --git a/TLB/test/test_cam_entry.py b/TLB/test/test_cam_entry.py
index 4ffcb72f..2f84596d 100644
--- a/TLB/test/test_cam_entry.py
+++ b/TLB/test/test_cam_entry.py
@@ -122,6 +122,14 @@ def testbench(dut):
     yield from set_cam_entry(dut, command, key, data)
     yield from check_all(dut, key, data, match, 0, 0, 0) 
     
+    # Check reset
+    command = 3
+    key = 0
+    data = 0
+    match = 0
+    yield from set_cam_entry(dut, command, key, data)
+    yield from check_all(dut, key, data, match, 0, 0, 0)     
+    
     # Extra clock cycle for waveform
     yield