From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 18:01:09 +0000 (+0200)
Subject: Merge pull request #953 from YosysHQ/clifford/fix948
X-Git-Tag: yosys-0.9~175
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3be5aac52c8703aa00ff591fd184da1ac39df678;p=yosys.git

Merge pull request #953 from YosysHQ/clifford/fix948

Add support for zero-width signals to Verilog back-end
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3be5aac52c8703aa00ff591fd184da1ac39df678