From: lkcl <lkcl@web>
Date: Sat, 29 Apr 2023 14:24:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bf66c5aa1dab18d203ea176431d5a127f2004ad;p=libreriscv.git

---

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index dc141055c..8d11350bd 100644
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -215,3 +215,95 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI VXIMZ
 ```
+
+## [DRAFT] Floating Add FFT/DCT [Single]
+
+A-Form
+
+* ffadds FRT,FRA,FRB (Rc=0)
+* ffadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRT <- FPADD32(FRA, FRB)
+    FRS <- FPSUB32(FRB, FRA)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+```
+
+## [DRAFT] Floating Add FFT/DCT [Double]
+
+A-Form
+
+* ffadd FRT,FRA,FRB (Rc=0)
+* ffadd. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRT <- FPADD64(FRA, FRB)
+    FRS <- FPSUB64(FRB, FRA)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+```
+
+## [DRAFT] Floating Subtract FFT/DCT [Single]
+
+A-Form
+
+* ffsubs FRT,FRA,FRB (Rc=0)
+* ffsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRT <- FPSUB32(FRB, FRA)
+    FRS <- FPADD32(FRA, FRB)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+```
+
+## [DRAFT] Floating Subtract FFT/DCT [Double]
+
+A-Form
+
+* ffsub FRT,FRA,FRB (Rc=0)
+* ffsub. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRT <- FPSUB64(FRB, FRA)
+    FRS <- FPADD64(FRA, FRB)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+```