From: Xan Date: Wed, 25 Apr 2018 12:02:30 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5513 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bf6704bc2a41d9a83d77dd5490018c9519f418e;p=libreriscv.git --- diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index f6dde6311..f2e7287e9 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -2,7 +2,7 @@ Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification. -An example use case is a string copy operation - using Harmonised RVP, binary code using SIMD instructions operating on integer registers to copy a string can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy the string. Harmonised RVP also upwards compatibility between RV32 and RV64 SIMD using this same approach. +An example use case is a string copy operation - using Harmonised RVP, code can use integer register SIMD instructions to copy a string. This code can then also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy the string. Harmonised RVP also upwards compatibility between RV32 and RV64 SIMD using this same approach. ## Register file comparison