From: whitequark <whitequark@whitequark.org>
Date: Thu, 4 Jun 2020 11:23:06 +0000 (+0000)
Subject: Merge pull request #2006 from jersey99/signed-in-rtlil-wire
X-Git-Tag: working-ls180~510
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3bffd09d6423b70ca154527c363985ff048f807d;p=yosys.git

Merge pull request #2006 from jersey99/signed-in-rtlil-wire

Preserve 'signed'-ness of a verilog wire through RTLIL
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3bffd09d6423b70ca154527c363985ff048f807d