From: lkcl <lkcl@web>
Date: Sat, 2 Oct 2021 22:25:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3752
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c05c9fac93b788c83b9f1da9823bd05669b77fc;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index 1cf9a37c9..2ef2b6929 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -180,6 +180,11 @@ This means one of two things:
   that they *pass through* SIMD behaviour entirely to a lower level,
   *completely intact*.
 
+Method (2) allows the Liskov Substitution Principle to be
+put to surprisingly good effect. If that was possible to
+achieve then **almost no modifications to nmigen would
+be required**.
+
 Analysis of the internals of nmigen shows that m.If, m.Else, m.FSM and m.Switch are all redirected to ast.py `Switch`.  Within that function Mux and other "global" functions (similar to python operator functions).  The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed.
 
 <https://github.com/nmigen/nmigen/blob/59ef6e6a1c4e389a41148554f2dd492328820ecd/nmigen/hdl/dsl.py#L447>