From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 23:25:59 +0000 (-0700)
Subject: Fix ordering of when to insert zero index
X-Git-Tag: yosys-0.9~171^2~9^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c1f1a6605a4463117ba358fc9528c4999628b81;p=yosys.git

Fix ordering of when to insert zero index
---

diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc
index f8cdf5783..6ffc27a4c 100644
--- a/passes/techmap/pmux2shiftx.cc
+++ b/passes/techmap/pmux2shiftx.cc
@@ -65,8 +65,7 @@ struct Pmux2ShiftxPass : public Pass {
 			const int clog2width = ceil(log2(s_width));
 
 			RTLIL::SigSpec pmux_b;
-			pmux_b.append(RTLIL::Const(0, clog2width));
-			for (int i = s_width-1; i > 0; i--)
+			for (int i = s_width-1; i >= 0; i--)
 				pmux_b.append(RTLIL::Const(i, clog2width));
 			shiftx_a.append(cell->getPort("\\B"));
 			pmux_s.append(cell->getPort("\\S"));