From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 7 Jul 2020 14:17:20 +0000 (+0200)
Subject: Update cke => clk_en in test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c2f1be9d2112df031ad6e73740b1fe985cb29ee;p=gram.git

Update cke => clk_en in test
---

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 475e980..6bb238e 100644
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -128,17 +128,17 @@ class DFIInjectorTestCase(FHDLTestCase):
 
         return (m, dut, csrhost)
 
-    def test_cke(self):
+    def test_clk_en(self):
         m, dut, csrhost = self.generate_dfiinjector()
 
         def process():
             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 1), sel=0xF)
             yield
-            self.assertTrue((yield dut.master.phases[0].cke[0]))
+            self.assertTrue((yield dut.master.phases[0].clk_en[0]))
 
             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF)
             yield
-            self.assertFalse((yield dut.master.phases[0].cke[0]))
+            self.assertFalse((yield dut.master.phases[0].clk_en[0]))
 
         runSimulation(m, process, "test_dfiinjector.vcd")