From: whitequark <whitequark@whitequark.org>
Date: Wed, 8 Jul 2020 07:12:00 +0000 (+0000)
Subject: back.pysim: reset timeline as well.
X-Git-Tag: 24jan2021_ls180~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c3cfd48fbc11fe94b87af613069fcb2dbf53cbd;p=nmigen.git

back.pysim: reset timeline as well.

This is a bug that was introduced in 94faf497b.
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 71b1b95..155a649 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -221,6 +221,7 @@ class _SimulatorState:
         self.pending  = set()
 
     def reset(self):
+        self.timeline.reset()
         for signal, index in self.signals.items():
             self.slots[index].curr = self.slots[index].next = signal.reset
         self.pending.clear()