From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 06:52:54 +0000 (+0200)
Subject: Test muxes synth one by one
X-Git-Tag: working-ls180~989^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c40c810307c2bed62527f4f067790edc4ac8823;p=yosys.git

Test muxes synth one by one
---

diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v
index 0814b733e..782424a9b 100644
--- a/tests/ecp5/mux.v
+++ b/tests/ecp5/mux.v
@@ -64,37 +64,3 @@ assign Y = D[S];
 
 endmodule
 
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys
index 7d40c9cf1..eada276ba 100644
--- a/tests/ecp5/mux.ys
+++ b/tests/ecp5/mux.ys
@@ -1,11 +1,46 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT4
+select -assert-none t:LUT4 %% t:* %D
+
+design -load read
+proc
+hierarchy -top mux4
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:L6MUX21
+select -assert-count 4 t:LUT4
+select -assert-count 2 t:PFUMX
+
+select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:L6MUX21
+select -assert-count 7 t:LUT4
+select -assert-count 2 t:PFUMX
+
+select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
+
+design -load read
 proc
-flatten
+hierarchy -top mux16
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 32 t:LUT4
+cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 8 t:L6MUX21
-select -assert-count 14 t:PFUMX
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D