From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Jul 2020 12:53:28 +0000 (+0100)
Subject: make cxxsim optional and print warning
X-Git-Tag: semi_working_ecp5~659
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c425869fd36a73a040e07b58050069c6022b0de;p=soc.git

make cxxsim optional and print warning
---

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index a8a62f1c..d905f68c 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -1,8 +1,15 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
-cxxsim = True
+# NOTE: to use this (set to True), at present it is necessary to check
+# out the cxxsim nmigen branch
+cxxsim = False
 if cxxsim:
-    from nmigen.sim.cxxsim import Simulator
+    try:
+        from nmigen.sim.cxxsim import Simulator
+    except ImportError:
+        print("nope, sorry, have to use nmigen cxxsim branch for now")
+        cxxsim = False
+        from nmigen.back.pysim import Simulator
 else:
     from nmigen.back.pysim import Simulator
 
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index fdb2089a..4abdfd12 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,10 +1,18 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
+# NOTE: to use this (set to True), at present it is necessary to check
+# out the cxxsim nmigen branch
 cxxsim = False
 if cxxsim:
-    from nmigen.sim.cxxsim import Simulator
+    try:
+        from nmigen.sim.cxxsim import Simulator
+    except ImportError:
+        print("nope, sorry, have to use nmigen cxxsim branch for now")
+        cxxsim = False
+        from nmigen.back.pysim import Simulator
 else:
     from nmigen.back.pysim import Simulator
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest