From: lkcl Date: Thu, 10 Dec 2020 15:02:27 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1436 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c4ff5c1761d331312f7575491972bdaf64e1ce4;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 6a474d623..296cd5254 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -54,7 +54,7 @@ For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/s One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation. This for Audio is extremely important, also to provide an indicator as to whether saturation occurred. see [[av_opcodes]]. -If there are spare bits it would be very good to look at using some of thrm to specify the mide, because otherwise a SPR has to be used which will need to be set and unset. This can get costly. +If there are spare bits it would be very good to look at using some of them to specify the mode, because otherwise a SPR has to be used which will need to be set and unset. This can get costly. # Notes about Swizzle