From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 16 May 2020 21:50:46 +0000 (-0400)
Subject: Add ilang output to test_maskgen.py
X-Git-Tag: div_pipeline~1122
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c65f5ff7893bb34696c476abacfe34ad739bf18;p=soc.git

Add ilang output to test_maskgen.py
---

diff --git a/src/soc/shift_rot/test/test_maskgen.py b/src/soc/shift_rot/test/test_maskgen.py
index f9d28d70..1a4d34e6 100644
--- a/src/soc/shift_rot/test/test_maskgen.py
+++ b/src/soc/shift_rot/test/test_maskgen.py
@@ -1,6 +1,7 @@
 from nmigen import Signal, Module
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
+from nmigen.cli import rtlil
 from soc.alu.maskgen import MaskGen
 from soc.decoder.helpers import MASK
 import random
@@ -37,5 +38,11 @@ class MaskGenTestCase(FHDLTestCase):
         with sim.write_vcd("maskgen.vcd", "maskgen.gtkw", traces=dut.ports()):
             sim.run()
 
+    def test_ilang(self):
+        dut = MaskGen(64)
+        vl = rtlil.convert(dut, ports=dut.ports())
+        with open("maskgen.il", "w") as f:
+            f.write(vl)
+
 if __name__ == '__main__':
     unittest.main()