From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 1 Sep 2019 14:34:28 +0000 (+0100)
Subject: add comp.arch link
X-Git-Tag: convert-csv-opcode-to-binary~4175
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c766991cc47d042d0e587112b8672027161d445;p=libreriscv.git

add comp.arch link
---

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 9fe4a5722..aea6bf4e2 100644
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -96,3 +96,6 @@ Twin-SVP mode allows certain registers to be explicitly marked as "scalar",
 where some of the rules might otherwise start to cascade through and cause
 registers to be come undesirably marked as "vectors".
 
+# Discussion
+
+* <https://groups.google.com/forum/#!topic/comp.arch/l2nzme2sCR0>