From: XiaoYuan Zheng <xiaoyuan.zheng@amd.com>
Date: Thu, 26 Jun 2014 07:47:51 +0000 (-0400)
Subject: amdgpu/addrlib: add new flag nonSplit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c7bd4e013735266bb140ccad0d1e69cfad418b2;p=mesa.git

amdgpu/addrlib: add new flag nonSplit

Flag tcCompatible has different usage in CI and VI. Add a new flag
"nonSplit" for CI.
---

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index ead603378cf..98cd405f594 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -456,7 +456,8 @@ typedef union _ADDR_SURFACE_FLAGS
         UINT_32 czDispCompatible: 1; ///< SI+: CZ family (Carrizo) has a HW bug needs special alignment.
                                      ///<      This flag indicates we need to follow the alignment with
                                      ///<      CZ families or other ASICs under PX configuration + CZ.
-        UINT_32 reserved      :10; ///< Reserved bits
+        UINT_32 nonSplit      : 1; ///< CI: depth texture should not be split
+        UINT_32 reserved      : 9; ///< Reserved bits
     };
 
     UINT_32 value;
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 26c4e056177..5f8a1fee527 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1010,7 +1010,7 @@ VOID CiAddrLib::HwlSetupTileInfo(
         // See table entries 0-4
         if (flags.depth || flags.stencil)
         {
-            if (flags.depth && flags.tcCompatible)
+            if (flags.depth && (flags.nonSplit || flags.tcCompatible))
             {
                 // tileSize = bpp * numSamples * 8 * 8 / 8
                 UINT_32 tileSize = bpp * numSamples * 8;