From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Oct 2018 13:16:14 +0000 (+0000)
Subject: redirect mmu load function(s) through sv_proc_t
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c8427c8322f0cb331a6ecda5edf3e325ff37a82;p=riscv-isa-sim.git

redirect mmu load function(s) through sv_proc_t
---

diff --git a/riscv/mmu.h b/riscv/mmu.h
index fc8d5b3..e3e8d0b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -360,6 +360,7 @@ private:
   trigger_matched_t *matched_trigger;
 
   friend class processor_t;
+  friend class sv_mmu_t;
 };
 
 struct vm_info {
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 90eaf24..3ee1ad8 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -923,3 +923,10 @@ sv_float128_t sv_proc_t::f64_to_f128( sv_float64_t a)
     return ::f64_to_f128(a);
 }
 
+//-----
+
+sv_reg_t sv_proc_t::adjust_load(sv_reg_t const& v, size_t width, bool ext)
+{
+    return v;
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index a23d1bd..30a00bc 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -266,6 +266,7 @@ public:
 
     sv_freg_t fsgnj128(sv_freg_t a, sv_freg_t b, bool n, bool x);
 
+    sv_reg_t adjust_load(sv_reg_t const& v, size_t width, bool ext);
 
 #include "sv_insn_decl.h"
 };
diff --git a/riscv/sv_mmu.cc b/riscv/sv_mmu.cc
index 4205397..fa20651 100644
--- a/riscv/sv_mmu.cc
+++ b/riscv/sv_mmu.cc
@@ -1,22 +1,22 @@
 #include "sv_mmu.h"
 
-#define sv_load_func(type) \
+#define sv_load_func(type, ext) \
 sv_reg_t sv_mmu_t::load_##type(reg_t const& addr) { \
   type##_t v = mmu_t::load_##type(addr); \
-  return sv_reg_t(v); \
+  return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
 } 
 
 // load value from memory at aligned address; zero extend to register width
-sv_load_func(uint8)
-sv_load_func(uint16)
-sv_load_func(uint32)
-sv_load_func(uint64)
+sv_load_func(uint8, true )
+sv_load_func(uint16, true )
+sv_load_func(uint32, true )
+sv_load_func(uint64, true )
 
 // load value from memory at aligned address; sign extend to register width
-sv_load_func(int8)
-sv_load_func(int16)
-sv_load_func(int32)
-sv_load_func(int64)
+sv_load_func(int8, false )
+sv_load_func(int16, false )
+sv_load_func(int32, false )
+sv_load_func(int64, false )
 
 #define sv_store_func(type) \
 void sv_mmu_t::store_##type(sv_reg_t const& addr, type##_t val) { \