From: Uros Bizjak Date: Wed, 29 Apr 2015 18:53:19 +0000 (+0200) Subject: re PR target/65871 (bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3c908a5b5c5bf5693dd2c5a3f1858867d1b96034;p=gcc.git re PR target/65871 (bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag) PR target/65871 * config/i386/i386.md (*bmi_bextr__cczonly): New pattern. (*bmi2_bzhi_3_1_cczonly): Ditto. testsuite/ChangeLog: PR target/65871 * gcc.target/i386/pr65871-1.c: New test * gcc.target/i386/pr65871-2.c: Ditto. From-SVN: r222588 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d7455e4e0a5..4c95a75b668 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-04-29 Uros Bizjak + + PR target/65871 + * config/i386/i386.md (*bmi_bextr__cczonly): New pattern. + (*bmi2_bzhi_3_1_cczonly): Ditto. + 2015-04-29 Thomas Schwinge PR libgomp/65099 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 937871a5af5..060ffa8ab84 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12594,6 +12594,20 @@ (set_attr "btver2_decode" "direct, double") (set_attr "mode" "")]) +(define_insn "*bmi_bextr__cczonly" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m") + (match_operand:SWI48 2 "register_operand" "r,r")] + UNSPEC_BEXTR) + (const_int 0))) + (clobber (match_scratch:SWI48 0 "=r,r"))] + "TARGET_BMI" + "bextr\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "direct, double") + (set_attr "mode" "")]) + (define_insn "*bmi_blsi_" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -12667,6 +12681,7 @@ (set_attr "mode" "")]) (define_mode_attr k [(SI "k") (DI "q")]) + (define_insn "*bmi2_bzhi_3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 @@ -12682,6 +12697,23 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) +(define_insn "*bmi2_bzhi_3_1_cczonly" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (zero_extract:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm") + (umin:SWI48 + (zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r")) + (match_operand:SWI48 3 "const_int_operand" "n")) + (const_int 0)) + (const_int 0))) + (clobber (match_scratch:SWI48 0 "=r"))] + "TARGET_BMI2 && INTVAL (operands[3]) == * BITS_PER_UNIT" + "bzhi\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "bitmanip") + (set_attr "prefix" "vex") + (set_attr "mode" "")]) + (define_insn "bmi2_pdep_3" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7ff95665c48..9d428f83aec 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2015-04-29 Uros Bizjak + + PR target/65871 + * gcc.target/i386/pr65871-1.c: New test + * gcc.target/i386/pr65871-2.c: Ditto. + 2015-04-29 Marek Polacek PR c/64610 diff --git a/gcc/testsuite/gcc.target/i386/pr65871-1.c b/gcc/testsuite/gcc.target/i386/pr65871-1.c new file mode 100644 index 00000000000..d76181e27a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65871-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ + +int foo (unsigned int x, unsigned int y) +{ + if (__builtin_ia32_bextr_u32 (x, y)) + return 1; + + return 0; +} + +/* { dg-final { scan-assembler-not "test" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr65871-2.c b/gcc/testsuite/gcc.target/i386/pr65871-2.c new file mode 100644 index 00000000000..e6538cc4bde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65871-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2" } */ + +int foo (unsigned int x, unsigned int y) +{ + if (__builtin_ia32_bzhi_si (x, y)) + return 1; + + return 0; +} + +/* { dg-final { scan-assembler-not "test" } } */