From: Segher Boessenkool Date: Tue, 2 Sep 2014 11:23:20 +0000 (+0200) Subject: rs6000.md (QHSI): Delete. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3cbab4af8022564e7ec3849e13ce5b9d5b814abe;p=gcc.git rs6000.md (QHSI): Delete. 2014-09-02 Segher Boessenkool * config/rs6000/rs6000.md (QHSI): Delete. (EXTQI, EXTHI, EXTSI): New mode iterators. (zero_extenddi2, *zero_extenddi2_internal1, *zero_extenddi2_internal2, *zero_extenddi2_internal3, *zero_extendsidi2_lfiwzx, zero_extendqisi2, zero_extendhisi2, 9 anonymous instructions, and 8 splitters): Delete. (zero_extendqi2, *zero_extendqi2_dot, *zero_extendqi2_dot2, zero_extendhi2, *zero_extendhi2_dot, *zero_extendhi2_dot2, zero_extendsi2, *zero_extendsi2_dot, *zero_extendsi2_dot2): New. From-SVN: r214815 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 79fb3f84aa5..c99c27008d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2014-09-02 Segher Boessenkool + + * config/rs6000/rs6000.md (QHSI): Delete. + (EXTQI, EXTHI, EXTSI): New mode iterators. + (zero_extenddi2, *zero_extenddi2_internal1, + *zero_extenddi2_internal2, *zero_extenddi2_internal3, + *zero_extendsidi2_lfiwzx, zero_extendqisi2, zero_extendhisi2, + 9 anonymous instructions, and 8 splitters): Delete. + (zero_extendqi2, *zero_extendqi2_dot, + *zero_extendqi2_dot2, zero_extendhi2, + *zero_extendhi2_dot, *zero_extendhi2_dot2, + zero_extendsi2, *zero_extendsi2_dot, + *zero_extendsi2_dot2): New. + 2014-09-02 Segher Boessenkool * config/rs6000/rs6000.md (any_extend): New code iterator. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f9e1ebaa2d7..6cd64042c9d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -309,8 +309,14 @@ ; Any supported integer mode that fits in one register. (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) -; extend modes for DImode -(define_mode_iterator QHSI [QI HI SI]) +; Everything we can extend QImode to. +(define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")]) + +; Everything we can extend HImode to. +(define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")]) + +; Everything we can extend SImode to. +(define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")]) ; QImode or HImode for small atomic ops (define_mode_iterator QHI [QI HI]) @@ -564,79 +570,112 @@ ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. -(define_expand "zero_extenddi2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))] - "TARGET_POWERPC64" - "") - -(define_insn "*zero_extenddi2_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] - "TARGET_POWERPC64 && (mode != SImode || !TARGET_LFIWZX)" +(define_insn "zero_extendqi2" + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] + "" "@ - lz%U1%X1 %0,%1 - rldicl %0,%1,0," + lbz%U1%X1 %0,%1 + rlwinm %0,%1,0,0xff" [(set_attr "type" "load,shift")]) -(define_insn "*zero_extenddi2_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) +(define_insn_and_split "*zero_extendqi2_dot" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] - "TARGET_64BIT" + (clobber (match_scratch:EXTQI 0 "=r,r"))] + "rs6000_gen_cell_microcode" "@ - rldicl. %2,%1,0, + andi. %0,%1,0xff #" - [(set_attr "type" "shift") + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) +(define_insn_and_split "*zero_extendqi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) + (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTQI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + andi. %0,%1,0xff + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + + +(define_insn "zero_extendhi2" + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] + "" + "@ + lhz%U1%X1 %0,%1 + rlwinm %0,%1,0,0xffff" + [(set_attr "type" "load,shift")]) -(define_insn "*zero_extenddi2_internal3" +(define_insn_and_split "*zero_extendhi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) + (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI (match_dup 1)))] - "TARGET_64BIT" + (clobber (match_scratch:EXTHI 0 "=r,r"))] + "rs6000_gen_cell_microcode" "@ - rldicl. %0,%1,0, + andi. %0,%1,0xffff #" - [(set_attr "type" "shift") + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTHI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) +(define_insn_and_split "*zero_extendhi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" + (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTHI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + andi. %0,%1,0xffff + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" [(set (match_dup 0) - (zero_extend:DI (match_dup 1))) + (zero_extend:EXTHI (match_dup 1))) (set (match_dup 2) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) -(define_insn "*zero_extendsidi2_lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") - (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] - "TARGET_POWERPC64 && TARGET_LFIWZX" + +(define_insn "zero_extendsi2" + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") + (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] + "" "@ lwz%U1%X1 %0,%1 rldicl %0,%1,0,32 @@ -645,6 +684,48 @@ lxsiwzx %x0,%y1" [(set_attr "type" "load,shift,mffgpr,fpload,fpload")]) +(define_insn_and_split "*zero_extendsi2_dot" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:EXTSI 0 "=r,r"))] + "rs6000_gen_cell_microcode" + "@ + rldicl. %0,%1,0,32 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:DI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + +(define_insn_and_split "*zero_extendsi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTSI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + rldicl. %0,%1,0,32 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTSI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + + (define_insn "extendqidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] @@ -867,74 +948,6 @@ (const_int 0)))] "") -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lbz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "extendqisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -995,68 +1008,6 @@ (const_int 0)))] "") -(define_insn "" - [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lbz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:HI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:HI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:HI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") - (zero_extend:HI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "") - (zero_extend:HI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "extendqihi2" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") @@ -1117,74 +1068,6 @@ (const_int 0)))] "") -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lhz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xffff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xffff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xffff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_expand "extendhisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "")