From: lkcl <lkcl@web>
Date: Tue, 14 Mar 2023 14:20:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~170
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3cbd7d5054ecbe564c7cc645ed46e48130e3a024;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index 9526daa07..abd02f5f5 100644
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -275,6 +275,32 @@ ternlogi r3, r4, r6, 0b11011000
 
 \newpage{}
 
+## crbinlog
+
+With ternary (LUT3) dynamic instructions being very costly,
+and CR Fields being only 4 bit, a binary (LUT2) variant is better
+
+| 0.5|6.8 | 9.11|12.14|15.17|18.21|22...30  |31|
+| -- | -- | --- | --- | --- |-----| -------- |--|
+| NN | BT | BA  | BB  | BC  |m0-m3|000101110 |0 |
+
+    mask = m0..m3
+    for i in range(4):
+        a,b = CRs[BA][i], CRs[BB][i])
+        if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
+
+When SVP64 Vectorised any of the 4 operands may be Scalar or
+Vector, including `BC` meaning that multiple different dynamic
+lookups may be performed with a single instruction.
+
+*Programmer's note: just as with binlut and ternlogi, a pair
+ of crbinlog instructions followed by a merging crternlogi may
+ be deployed to synthesise dynamic ternary (LUT3) CR Field
+ manipulation*
+
+----------
+
+\newpage{}
 
 ----------