From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Wed, 17 Jun 2020 20:28:56 +0000 (+0000)
Subject: rtlil: Add `Design::select()` for selecting whole modules.
X-Git-Tag: working-ls180~458^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ccdab940cd054d996a5ce94010918edd782cae0;p=yosys.git

rtlil: Add `Design::select()` for selecting whole modules.
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f3dc3af68..354823e3b 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1061,6 +1061,13 @@ struct RTLIL::Design
 		return selected_member(module->name, member->name);
 	}
 
+	template<typename T1> void select(T1 *module) {
+		if (selection_stack.size() > 0) {
+			RTLIL::Selection &sel = selection_stack.back();
+			sel.select(module);
+		}
+	}
+
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
 		if (selection_stack.size() > 0) {
 			RTLIL::Selection &sel = selection_stack.back();