From: lkcl <lkcl@web>
Date: Sat, 9 Apr 2022 21:21:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2816
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3cd7ccba0843d8a919bff1cbabfded6519524573;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index be12ba2c5..ef232e846 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -120,6 +120,13 @@ in the decoder is greatly increased.
 
 # EXTRA Field Mapping
 
+The purpose of the 9-bit EXTRA field mapping is to mark individual
+registers (RT, RA, BFA) as either scalat or vector, and to extend
+their numbering from 0..31 in Power ISA v3.0 to 0..127 in SVP64.
+Three of the 9 bits may also be used up for a 2nd Predicate (Twin
+Predication) leaving a mere 6 bits for qualifying registers. As can
+be seen there is significant pressure on these (and all) SVP64 bits.
+
 In Power ISA v3.1 prefixing there are bits which describe and classify
 the prefix in a fashion that is independent of the suffix. MLSS for
 example.  For SVP64 there is insufficient space to make the SVP64 Prefix