From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 14 Jul 2020 16:09:11 +0000 (+0100)
Subject: arch-arm: AddressSize check on translateMmuOff for AArch64 only
X-Git-Tag: v20.1.0.0~466
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ce7333a3619448a34bfb0c24f111e4473c3272c;p=gem5.git

arch-arm: AddressSize check on translateMmuOff for AArch64 only

Motivation:
An AddressSizeFault on AArch32 can only happen during a table walk
since the register used as a base by LD/ST is always 32 bit wide.
On AArch64 on the other hand, addresses can be 64bit wide;
when MMU is off (no virtual memory) an invalid physical address
can be specified

Change-Id: Id3ef170e99202c6b0b511fa7205c754956861720
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31274
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index db0d55c97..ca9784935 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1018,21 +1018,23 @@ TLB::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
     if (isSecure)
         req->setFlags(Request::SECURE);
 
-    bool selbit = bits(vaddr, 55);
-    TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
-    int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
-    int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
-    if (addr_sz != 0){
-        Fault f;
-        if (is_fetch)
-            f = std::make_shared<PrefetchAbort>(vaddr,
-                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
-        else
-            f = std::make_shared<DataAbort>( vaddr,
-                TlbEntry::DomainType::NoAccess,
-                is_atomic ? false : mode==Write,
-                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
-        return f;
+    if (aarch64) {
+        bool selbit = bits(vaddr, 55);
+        TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+        int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+        int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+        if (addr_sz != 0){
+            Fault f;
+            if (is_fetch)
+                f = std::make_shared<PrefetchAbort>(vaddr,
+                    ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+            else
+                f = std::make_shared<DataAbort>( vaddr,
+                    TlbEntry::DomainType::NoAccess,
+                    is_atomic ? false : mode==Write,
+                    ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+            return f;
+        }
     }
 
     // @todo: double check this (ARM ARM issue C B3.2.1)