From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Sep 2022 16:03:58 +0000 (+0100)
Subject: frickin frick
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ce758297aa846dd353f8bfe79ab4eeb80db4233;p=openpower-isa.git

frickin frick
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 58cf4f1b..cf26f43f 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1147,14 +1147,11 @@ class SVP64Asm:
             elif encmode == 'vli':
                 assert sv_mode == 0b01 # only allow ff mode
                 vli = True
-<<<<<<< HEAD
-=======
             elif encmode == 'sea':
                 assert sv_mode in (None, 0b00, 0b01)
                 assert rm['mode'] == "LDST_IDX"
                 sea = True
                 assert failfirst is False, "cannot use ffirst+signed-address"
->>>>>>> 54866195 (add asserts to ensure failfirst+sea not attempted)
             elif is_bc:
                 if encmode == 'all':
                     svp64_rm.branch.ALL = 1