From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 21:54:24 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux_wip
X-Git-Tag: working-ls180~1208^2~112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3cf2afc2802e32288b2f83da6ebe4b4fbfa8e013;p=yosys.git

Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux_wip
---

3cf2afc2802e32288b2f83da6ebe4b4fbfa8e013
diff --cc CHANGELOG
index 1ab1bc4f2,db7e14957..24c81be6e
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -17,15 -17,8 +17,16 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
 +    - Added "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Extended "muxcover -mux{4,8,16}=<cost>"
 +    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 +    - Added "synth -abc9" (experimental)
+     - Added "muxpack" pass
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8