From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 12:39:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2924
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d064665481980294332905843e97499d882b53c;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 62a39b198..4f15ff92f 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -9,8 +9,8 @@ standard scalar OpenPOWER-approved v3.0B branches.
 **v3.0B branches are in no way impacted, altered,
 changed or modified in any way, shape or form by
 the SVP64 Vectorised Variants**.  It is
-extremely important to note that this is the one
-sole semi-exception in SVPY4 to `Scalar Identity Behaviour`.
+extremely important to note that Branches are the one
+sole semi-exception in SVP64 to `Scalar Identity Behaviour`.
 SVP64 Branches contain additional modes that are useful
 for scalar operations (i.e. even when VL=1).
 
@@ -463,6 +463,9 @@ This contrivance is avoided by the behavioural inversion bits.
 
 # Pseudocode and examples
 
+Please see [[svp64/appendix]] regarding CR bit ordering and for
+the definition of `CR{n}`
+
 For comparative purposes this is a copy of the v3.0B `bc` pseudocode
 
 ```